Method and apparatus for reconstructing the address of the next instruction to be completed in a pipelined processor

An apparatus for use in a computer processing unit for generating an address of the next instruction to be completed, said apparatus comprising:

• a first table for storing a plurality of entries each corresponding to a dispatched instruction, each entry comprising an identifier that identifies the associated instruction and a completion status field that indicates if the associated instruction is complete;
• a second table for storing a plurality of entries each corresponding to a dispatched branch instruction, each entry comprising the same identifier stored in said first table, a target address of the dispatched branch instruction and a resolution status field that indicates at least if the corresponding branch instruction has been resolved taken or has been resolved not taken;
• program counter update logic that, in each machine cycle, updates a program counter with the address of the next instruction to be completed according to said entries stored in said first table and said second table, wherein said program counter update logic in a given machine cycle,
• reads out at least one entry from said first table;
• and
• for each entry read from said first table whose completion status field indicates the associated instruction is completed, accesses said second table with the associated identifier of the entry to thereby determine said address of the next instruction to be completed in said computer processing unit.

A method of generating an address of the next instruction to be completed in a computer processing unit, the method comprising the steps of:

• for each instruction dispatched for execution,
• generating an identifier that identifies the instruction;
• adding an entry to a first table, wherein said entry of said first table comprises said identifier and a branch bit that indicates if the instruction is a branch instruction;
• if the instruction is a branch instruction, adding an entry to a second table, wherein said entry of said second table comprises said identifier, a target address of the instruction and a resolution status field that indicates at least if the instruction has been resolved taken or has been resolved not taken;
• updating the resolution status field of one or more entries of said second table according to resolution of branch instructions;
• and
• in each machine cycle, reading one or more entries from said first table,
• generating a completion status signal corresponding to each of said one or more entries read from said first table, wherein said completion status signal indicates if the instruction associated with each entry is completed, and
• controlling a program counter to generate the address of the next instruction to be completed according to said entries of said second table and said completion status signal.

An apparatus for use in a computer processing unit for generating an address of the next instruction to be completed, said apparatus comprising:

• a first table for storing a plurality of entries each corresponding to a dispatched instruction, each entry comprising an identifier that identifies the associated instruction and a branch bit that indicates if the associated instruction is a branch instruction;
• a second table for storing a plurality of entries each corresponding to a dispatched branch instruction, each entry comprising the same identifier stored in said first table, a target address of the dispatched branch instruction and a resolution status field that indicates at least if the corresponding branch instruction has been resolved taken or has been resolved not taken;
• means for generating, in each machine cycle, a completion status signal corresponding to one or more entries read from said first table that indicate if the instructions associated with said one or more entries are completed;
• program counter update logic that, in each machine cycle, updates a program counter with the address of the next instruction to be completed according to said entries stored in said second table and said completion status signal.