Apparatus and method for array bounds checking with a shadow register file

A method of processing source code with associated array bounds limitations, said method comprising the steps of:

• computing, with an array bounds check circuit, an effective memory address for an array value defined in a source code instruction, said computing including accessing a base memory address stored in a primary register and multiplying an array element size value by an array index value to obtain a memory block product;
• reading an array bound value from a shadow register location defined in said source code instruction;
• and
• generating a hardware error signal when said effective memory address exceeds said array bound value.

A method of processing computer instructions with associated array bounds limitations, comprising the steps of:

• accessing a base memory address;
• computing a memory block product from an array element size value and an array index value;
• adding said memory block product to said base memory address to yield an effective memory address;
• reading an array bound value;
• and
• generating an error signal when said effective memory address exceeds said array bound value.