System for fetching mapped branch target instructions of optimized code placed into a trace memory
AssigneeHewlett-Packard Company
InventorsWei C. Hsu, Manuel Benitez
Life of this patent
Estimating the term…
Abstract
The inventive mechanism uses a cache table to map branch targets. When a fetch instruction is initiated, the inventive mechanism searches the IP-to-TM cache to determine whether the branch target instruction has been optimized and placed into the trace memory. If there is a match with the IP-to-TM cache, then the code in the trace is executed. This cache is examined in parallel with Instruction Translation Lookup Buffer (ITLB). If not a match is found in the IP-to-TM cache, the original binary in the physical address provided by the ITLB will be executed.
Claims14
A hardware system for fetching an instruction for execution that corresponds to an instruction pointer in a program, wherein the program has at least one portion expressed in a first code and at least one portion expressed in a second code wherein the second code is comprised of instructions that has been optimized, the system comprising:
- a first memory portion for holding the first code;
- a second memory portion for holding the second code;
- a third memory portion for holding an active portion of a mapping of instruction pointers to addresses of instructions of the second code in the second memory portion;
- a fourth memory portion that holds a mapping of instruction pointers to addresses of instructions of the first code in the first memory position;
- and
- a processor sub-unit for determining whether the instruction pointer is an address in the second memory portion;
- wherein if the instruction pointer is an address in the second memory portion, the processor sub-unit fetches the instruction in the second code corresponding to the address in the second memory portion for execution;
- and
- wherein if the instruction pointer is not an address in the second memory portion, the processor sub-unit performs a parallel search of the third memory portion to determine whether the instruction pointer has a mapping to a corresponding instruction in the second code, and the fourth memory portion to determine whether the instruction pointer has a mapping to a corresponding instruction in the first memory portion, wherein an address match in the fourth memory portion is ignored in favor of an address match in the third memory portion,
- if the instruction pointer has a mapping in the third memory portion, then the processor sub-unit fetches the instruction in the second code corresponding to the address in the second memory portion for execution, and
- if the instruction pointer does not have a mapping in the third memory portion, then the processor sub-unit fetches the instruction in the first code corresponding to the instruction pointer for execution.
A method using a hardware system for fetching an instruction for execution that corresponds to an instruction pointer in a program, wherein the program has at least one portion expressed in a first code and at least one portion expressed in a second code wherein the second code is comprised of instructions that has been optimized, the system includes a first memory portion for holding the first code, a second memory portion for holding the second code, a third memory portion for holding an active portion of a mapping of instruction pointers to addresses of instructions of the second code in the second memory portion, and a fourth memory portion that holds a mapping of instruction pointers to addresses of instructions of the first code in the first memory portion, the method comprising the steps of:
- determining whether the instruction pointer is an address in the second memory portion via a processor sub-unit;
- fetching the instruction in the second code corresponding to the address in the second memory portion for execution, via the processor sub-unit, if the instruction pointer is an address in the second memory portion;
- performing, via the processor sub-unit, a parallel search of the third memory portion to determine whether the instruction pointer has a mapping to a corresponding instruction in the second code, and the fourth memory portion to determine whether the instruction pointer has a mapping to a corresponding instruction in the first memory portion, if the instruction pointer is not an address in the second memory portion, wherein an address match in the fourth memory portion is ignored in favor of an address match in the third memory portion;
- fetching the instruction in the second code corresponding to the address in the second memory portion for execution, via the processor sub-unit, if the instruction pointer has a mapping in the third memory portion;
- and
- fetching the instruction in the first code corresponding to the instruction pointer for execution, via the processor sub-unit, if the instruction pointer does not have a mapping in the third memory portion.
Dependencies are inferred from the claim text.