Method and apparatus for speculative execution of instructions
AssigneeIntergraph Corporation
InventorSiamak Arya
Life of this patent
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Abstract
An apparatus and method are described for implementing handling of exceptions caused by speculated instructions in a CPU having speculative execution capabilities. A CPU implementing speculative execution contains a speculative bit register file. Each speculative bit in the speculative bit register file is logically associated with a particular general purpose register, while remaining physically separate. This is accomplished through the use of a physically separate register file (the speculative bit register file) and register selection circuitry allowing simultaneous access to the two register files. The present invention provides instruction execution hardware supporting speculative execution with minimal impact on computational and structural complexity.
Claims31
An apparatus for facilitating speculative execution of instructions in a data processing system, comprising:
- a register file comprising a plurality of registers, each one of the plurality of registers configured to store one of a plurality of instructions;
- a plurality of single-bit storage units disposed separately from the register file;
- a multiple bit write bus coupled to the plurality of single bit storage units;
- and
- a multiple bit read bus coupled to the plurality of single bit storage units;
- wherein each one of the plurality of single-bit storage units corresponds to one of the plurality of registers and is configured to store one of a plurality of speculative bits,
- wherein the plurality of single-bit storage units are configured to simultaneously receive and store the plurality of speculative bits;
- and
- wherein each one of the plurality of speculative bits is operable to indicate an occurrence of an exception, wherein each one of the plurality of speculative bits indicates the occurrence of the exception if the execution of an instruction stored in a corresponding register generates an exception.
An apparatus for facilitating speculative execution of instructions in a data processing system, comprising:
- a register file comprising a plurality of registers, each one of the plurality of registers configured to store one of a plurality of binary words;
- a plurality of single-bit storage units disposed separately from the register file;
- a multiple bit write bus coupled to the plurality of single-bit storage units configured to provide speculative bit inputs for a first group of single-bit storage units from the plurality of single-bit storage units;
- a multiple bit read bus coupled to the plurality of single-bit storage units configured to provide to speculative bit outputs from a second group of single-bit storage units;
- from the plurality of single-bit storage units;
- a single bit write bus coupled to the plurality of single-bit storage units configured to provide speculative bit input for a first single-bit storage unit from the plurality of single-bit storage units;
- a single bit read bus coupled to the plurality of single-bit storage units configured to provide speculative bit output from a second single-bit storage unit from the plurality of single-bit storage units;
- wherein each one of the plurality of single-bit storage units corresponds to one of the plurality of registers, and is configured to store one of a plurality of speculative bits,
- wherein each one of the plurality of speculative bits is operable to indicate an occurrence of an exception,
- wherein a given one of the plurality of speculative bits indicates the occurrence of the exception if the execution of an instruction generates the exception;
- and
- register selection circuitry coupled to the single bit read bus, to the single bit write bus, and to the register file configured to select specific ones of the plurality of registers and corresponding ones of the plurality of single-bit storage units for reading and writing operations.
A method for speculatively executing instructions in a data processing system, the data processing system including a register file comprising a plurality of registers, each one of the registers configured to store one of a plurality of binary words, the data processing system also including a plurality of single-bit storage units disposed separately from the register file, each single-bit storage unit being configured to store a speculative bit corresponding to one of the plurality of registers, the method comprising:
- speculatively executing an instruction in a target stream associated with a branch instruction and an instruction in a fall-through stream associated with the branch instruction;
- and
- for the executed instruction in the target stream and for the executed instruction in the fall-through stream, altering a speculative bit stored in a respective single-bit storage unit corresponding to the executed instructions to indicate an exception of each respective executed instruction,
- wherein altering the speculated bit comprises accessing a single-bit storage unit corresponding to the executed instruction in the target stream and accessing a single bit storage unit corresponding to the executed instruction in the fall-through stream substantially simultaneously via a multiple bit write bus coupled to the plurality of single bit storage units.
Dependencies are inferred from the claim text.