Input/output support for processing in a mesh connected computer
AssigneeTeraNex, Inc.
InventorsAndrew P. Abercrombie, Surachai Sutha, Wlodzimierz Holsztynski
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AssigneeTeraNex, Inc.
InventorsAndrew P. Abercrombie, Surachai Sutha, Wlodzimierz Holsztynski
Estimating the term…
An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a pattern register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming “supercells” within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register. These registers have bit values corresponding to respective columns (for the X Pattern register) and rows (for the Y Pattern register) of the array. Patterns can be propagated from these registers into corresponding rows and columns. Further these registers can be used to receive values representing the logical OR of signals generated by individual PEs within respective rows and columns. Further, a number of global data registers are used to store information which can be broadcast back into the processing array.
A parallel processor, comprising:
A parallel processor, comprising:
A method for processing data in parallel using a parallel processor, wherein said parallel processor comprises a plurality of processing elements (PEs) arranged in an array to form a PE array, wherein said PE array encompasses a plurality of sections, each section containing a group of PEs, said method comprising the steps of:
A method for processing data in parallel using a parallel processor, wherein said parallel processor comprises a plurality of processing elements (PEs) arranged in an array to form a PE array, wherein said PE array encompasses a plurality of sections, each section containing a group of PEs, and wherein each section has a register associated therewith, said method comprising the steps of:
Dependencies are inferred from the claim text.