Multi-way cache apparatus and method

An integrated circuit comprising:

• a cache having a first way and a second way;
• a first storage element for storing a first stored attribute for the first way of the cache;
• a second storage element for storing a second stored attribute for the second way of the cache;
• a conductor for transferring an access attribute;
• and
• control circuitry which compares the access attribute to the first stored attribute to provide a first comparison result and which selectively enables the first way of the cache based on the first comparison result, and which compares the access attribute to the second stored attribute to provide a second comparison result and which selectively enables the second way of the cache based on the second comparison result wherein the control circuitry selectively enables the first way of the cache and selectively enables the second way of the cache prior to determining if one of a cache hit and a cache miss has occurred.

An apparatus having a multi-way cache, comprising:

• a first user controllable element having a predetermined first attribute corresponding to a first way of the multi-way cache;
• a second user controllable element having a predetermined second attribute corresponding to a second way of the multi-way cache;
• a conductor for transferring an access attribute to the multi-way cache;
• first compare circuitry which compares the access attribute to the predetermined first attribute to provide a first comparison result;
• second compare circuitry which compares the access attribute to the predetermined second attribute to provide a second comparison result;
• first way control circuitry for selectively enabling the first way of the multi-way cache based on the first comparison result;
• and
• second way control circuitry for selectively enabling the second way of the multi-way cache based on the second comparison result;
• first way control circuitry for selectively enabling the first way of the multi-way cache based on the first comparison result;
• and
• second way control circuitry for selectively enabling the second way of the multi-way cache based on the second comparison result, wherein the first way control circuitry selectively enables the first way and the second way control circuitry selectively enables the second way prior to the apparatus determining if one of a cache hit and a cache miss, corresponding to the access operation, has occured.