US 6,185,652 B2 · Interrupt mechanism on NorthBay

Abstract

An interrupt tracking mechanism includes a CPU that handles interrupts generated by an interrupt generator, a storage element accessible to the CPU, an interrupt counter implemented in hardware and a single set of interrupt status-registers. The interrupts are generated by the interrupt generator in an order determined by the order of tasks sent by the CPU to the interrupt generator and indicate completion of those tasks. The CPU can maintain in the storage element an ordered list of at least a contiguous subset of the tasks sent to the interrupt generator. The CPU can also maintain in the storage element a count of tasks sent to the interrupt generator as part of the contiguous subset. For each interrupt it generates the interrupt generator increments the count in the interrupt counter and writes the address of the interrupt to the interrupt status register. Because a single interrupt status register is used, only the status information for the latest interrupt is available in the register. When it has time to respond to an interrupt the CPU reads then resets the interrupt counter and reads the interrupt status register to determine the current interrupt count and interrupt address. From the current interrupt count and address and the contents of the ordered list and the task count the CPU is able to determine with certainty how many tasks previously sent to the interrupt generator are pending and accordingly generate new tasks to keep the interrupt generator busy.

Claims7

Dependent claims

An interrupt handling mechanism for use with a computer-based system in which an interrupt generator issues interrupt requests that are serviced by an interrupt handler, comprising:

a group of ordered operations sent by the interrupt handler to the interrupt generator for execution;
the interrupt generator being configured to execute the ordered operations and issue an interrupt request following execution of a predetermined number of the ordered operations, the predetermined number ranging from one to all of the operations;
an interrupt tabulator including at least one of:
an interrupt counter that stores an interrupt count that is incremented by the interrupt handler each time the interrupt request is issued;
and
an interrupt address register in which the interrupt generator writes an interrupt address associated with a respective operation whose execution caused the interrupt request to be issued;
wherein
the interrupt handler is configured, whenever the interrupt handler services the interrupt generator, not necessarily in response to the interrupt request, to read the interrupt tabulator to determine processing status of interrupt generator, including:
when the interrupt tabulator incorporates the interrupt counter, reading the interrupt count;
when the interrupt tabulator incorporates the interrupt address register, reading the interrupt address;
and
based on the processing status of the interrupt generator, the interrupt handler is configured to determine which of the ordered operations are still pending for execution by the interrupt generator and to, as a result, send an additional group of ordered operations to the interrupt generator in order to keep the interrupt generator as busy as possible.

9 more elements

Dependencies are inferred from the claim text.

Interrupt mechanism on NorthBay

Life of this patent

Interrupt mechanism on NorthBay

Life of this patent

Abstract

Claims7