System for correcting an illegal addressing signal by changing a current bit from one to zero if a bit immediately left adjacent to the current bit is zero
AssigneeToshiba America Electronic Components, Inc.
InventorJohn M. Lo
Life of this patent
Estimating the term…
Abstract
An apparatus and a method detect and automatically correct an illegal address in a peripheral connect interface bus addressing scheme. The value of a current bit is read. The value of a bit immediately left adjacent of the current bit is read. A value of 0 is outputted as the current bit in the event the value of the current bit is 1 and the value of the left adjacent bit is 0. In one specific embodiment, the apparatus employs a multiplexer and a single-bit register with a feedback as a one bit detection and correction circuit.
Claims6
An apparatus to correct an illegal addressing signal comprising:
- means for reading a value of a current bit;
- means for reading a value of a left adjacent bit of said current bit;
- and
- means for outputting a value of 0 as said current bit in the event said value of said current bit is 1 and said value of said left adjacent bit is 0.
An apparatus to correct an illegal addressing signal comprising:
- a multiplexer;
- a single-bit register;
- a first selection line connecting an output of said single-bit register with the multiplexer;
- a first input line connecting the single-bit register with the multiplexer;
- a third input line connecting the single-bit register with the multiplexer;
- a second input line connected to ground having a level of 0;
- a fourth input line for supplying input data to said multiplexer;
- a second selection line connecting an output of an adjacent single bit register with the multiplexer;
- and
- an output line connecting the multiplexer with the single-bit register.
A method for correcting an illegal addressing signal comprising the steps of:
- inputing a current bit from a single-bit register to a multiplexer via a first selection line;
- inputing the current bit from the single-bit register to the multiplexer via a first input line and a third input line;
- inputing a left bit to the multiplexer via a second selection line, the left bit being a left adjacent bit of the current bit;
- inputing a value of 0 to the multiplexer via a second input line;
- selecting an input from the input lines for an output based on the inputs from the first and second selection lines;
- and
- sending the output to the single-bit register.
Dependencies are inferred from the claim text.