Memory system including a plurality of memory devices and a transceiver device

A memory system having a controller device coupled to a first bus, and a plurality of synchronous memory devices, the memory system comprising:

• a transceiver device connected to the first bus;
• a second bus connected to the first transceiver device, the second bus including a first clock line, and wherein the transceiver device is coupled between the second bus and the first bus;
• a first memory device having clock receiver circuitry and at least one memory section, wherein the clock receiver circuitry is connected to the first clock line;
• and
• a second memory device having clock receiver circuitry and at least one memory section, wherein the clock receiver circuitry is connected to the first clock line.

A memory module having a plurality of synchronous memory devices, each memory device having an array of memory cells, the memory module comprising:

• a bus having a plurality of signal lines, including a first clock line;
• a transceiver device coupled to the bus;
• a first synchronous memory device including:
• clock receiver circuitry, coupled to the first clock line, to receive a first clock signal;
• output driver circuitry coupled to the bus, to output data onto the bus synchronously with respect to the first clock signal;
• and
• a second synchronous memory device including:
• clock receiver circuitry, coupled to the first clock line, to receive a first clock signal;
• and
• output driver circuitry coupled to the bus, to output data onto the bus synchronously with respect to the first clock signal.