Bus for high frequency operation with backward compatibility and hot-plug ability

A computer system comprising:

• a system bus;
• a memory device connected to said system bus;
• processor means, connected to said system bus, for carrying out program instructions stored in said memory device;
• a bridge connected to said system bus, wherein said bridge is adapted to selectively operate in either a high performance mode or a low performance mode and includes a pin to receive an indication of whether said peripheral bus and said peripheral device may operate at a first operating speed and a second operating speed that is less than the first operating speed;
• a peripheral bus connected to said bridge, said peripheral bus operating at a particular data transmission rate;
• a peripheral device connected to said peripheral bus;
• means for determining when all of said peripheral device, said peripheral bus, and said bridge are adapted to operate at the first operating speed;
• and
• means for operating at said first operating speed by clocking data on both a rising edge and a falling edge of a clock signal.

A system for providing selectable operation protocols and associated data transmission speeds between a peripheral device and system bus of a computer system, said system comprising:

• a peripheral bus designed for transmitting data with at least one of multiple transmission speeds including a first transmission speed associated with a first protocol and a second transmission speed associated with a second protocol, wherein said second transmission speed is faster than said first transmission speed;
• a peripheral device connected to said peripheral bus, said peripheral device operating at one of said first transmission speed and said second transmission speed;
• a hot plug controller coupled to a plurality of slots utilized to connect said peripheral device to said peripheral bus and which monitors said device for operation characteristics including transmission speed;
• a bridge, coupled to said system bus and to said hot plug controller, said bridge including a control mechanism by which a transmission speed on said peripheral bus is selected for data transmission to and from said peripheral device based on operational limitations imposed by one or more of said peripheral device, peripheral bus, or bridge.

A method of providing backward compatibility for a high performance Peripheral Component Interconnect (PCI) bus within a data processing system, said method comprising the steps of:

• connecting a bridge to a system bus of said data processing system;
• connecting a PCI bus to said bridge;
• connecting a peripheral device to said peripheral bus;
• determining a performance mode common to all of said peripheral device, said PCI bus, and said bridge, wherein said performance mode transmits data at a particular speed utilizing an associated transmission protocol;
• and
• transmitting data between said bridge and said peripheral device utilizing said common performance mode, wherein when said performances mode is a low performance mode, said data is transmitted at a first speed with a standard transmission protocol and when said performance mode is a high performance mode, said data is transmitted at a second speed, which is faster than said first speed and with a second transmission protocol that operates the PCI bus at higher clock rates by prohibiting pacing between data cycles.