Dynamically allocating space in RAM shared between multiple USB endpoints and USB host

A USB microcontroller comprising:

• a first interface for interfacing with one of a USB host or USB hub,
• at least one second interface for interfacing with at least one peripheral device so that said peripheral device can be connected to said USB, and
• a memory management unit for use in a USB peripheral controller comprising a single RAM whose address space is dynamically allocatable between packets associated with a plurality of USB endpoints and packets associated with said USB host, and whose buffering is not limited to a first-in-first-out (FIFO) paradigm.

A USB microcontroller comprising:

• a first interface for interfacing with one of USB host or USB hub,
• a second interface for interfacing with at least one peripheral device and comprising first and second masters,
• a memory management unit connected to both said first and second interfaces, said memory management unit comprising a single RAM whose address space is dynamically allocated to packets directly received by the first and second interfaces, where the packets are associated with both a plurality of USB endpoints and said USB host, wherein said RAM is not limited to buffering said packets in a first-in-first-out (FIFO) paradigm, and an arbiter for enabling said first and second masters and a master associated with said first interface to access said RAM.

A memory management unit for a USB peripheral controller comprising a single RAM whose address space is dynamically allocatable between packets directly received from a plurality of USB endpoints and a USB host, a receive queue for queuing identifiers of said packets associated with said USB host, a transmit queue associated with each of said USB endpoints for queuing identifiers of said packets associated with the corresponding USB endpoint.

A USB peripheral microcontroller comprising:

• a Serial Input Engine for interfacing with one of a USB host or USB hub,
• an external device interface for interfacing with at least one peripheral device, and
• a memory management unit connected to said Serial Input Engine and said external device interface, said memory management unit comprising a RAM whose address space is dynamically allocated to packets generated at one or more USB endpoints associated with said at least one peripheral device and packets transmitted from said host via said USB hub, and whose buffering is not limited to a first-in-first-out (FIFO) paradigm.