DMA configurable receive channel with memory width N and with steering logic compressing N multiplexors

A method of optimizing a data transfer to an N-byte wide memory system within a data processing system from an M-byte wide receive buffer using a bus master controller, wherein the data includes a plurality of control bits and is organized in data frames, wherein each data frame is to be stored in one or more data buffers in the memory system, and wherein each data buffer includes an associated descriptor block having a memory system address pointer field for holding an address pointer, a length field for holding a length value, a status field for holding a status value, and a command field for holding a command value, the method comprising the steps of:

• initializing first and second latched storage registers capable of holding the least significant bits of the address pointer and the length value, which together indicate the alignment of the start and end of the data buffer relative to N-byte wide boundaries within the memory system, to zero;
• initializing third and fourth latched storage registers capable of holding intermediate values used to calculate the byte arrangement for transferring data into data buffers in the memory from the receive buffer;
• loading the descriptor block values including the address pointer to the next data buffer to be filled, the length value of the next data buffer to be filled, the status value of the next data buffer to be filled, and the command value of the next data buffer to be filled, into the bus master controller;
• loading and latching the first, second, third and fourth latched storage registers in response to loading the descriptor block values;
• calculating a steer value based upon the values stored in the latched storage registers;
• steering N bytes of the data into accumulator registers based upon the calculated steer value;
• calculating a shuffle steer value based upon the values stored in the latched storage registers;
• rearranging the data in the accumulator registers based upon the calculated shuffle steer value to align the data with the data buffer in memory;
• transferring the rearranged data from the accumulator registers into the current data buffer in memory;
• repeating the steps of loading the descriptor block values, loading and latching the first, second, third and fourth latched storage registers, calculating a steer value, steering N bytes of the data, calculating a shuffle steer value, rearranging the data in the accumulator registers, and transferring the rearranged data until the current data buffer is full;
• repeating the steps of initializing the first, second, third, and fourth latched storage registers, loading the descriptor block values, loading and latching the first, second, third and fourth latched storage registers, calculating a steer value, steering N bytes of the data, calculating a shuffle steer value, rearranging the data in the accumulator registers, and transferring the rearranged data until the entire frame is transferred from the receive buffer into one or more data buffers
• writing one or more place holder bytes into the data buffer after the end of the transferred data frame to insure that the frame ends within a data buffer on a memory width boundary;
• and
• writing a value into the status field of the descriptor block of the last data buffer of the transferred data frame to indicate that the frame has been transferred.