Method and apparatus for parallel normalization and rounding technique for floating point arithmetic operations

A system for normalization and rounding of an ANSI/IEEE 754-1985 floating point arithmetic intermediate result having a fraction and an exponent, comprising:

• an exponent logic circuit that always increments the exponent of the intermediate result;
• a fraction logic circuit that adjusts the fraction of the intermediate result, said fraction logic circuit further comprising a normalizer circuit that normalizes the fraction of the intermediate result, a rounder circuit that rounds the fraction of the intermediate result, and a select control circuit that selects one of a plurality of formatting procedures, where said formatting procedure selected uses the output from either said normalizer circuit or said rounder circuit to generate the result fraction in proper result mantissa in ANSI/IEEE 754-1985 format;
• and
• a control logic circuit that controls said exponent logic circuit and said fraction logic circuit and sets the round control bit.

A method to manufacture an apparatus that normalizes and rounds an ANSI/IEEE 754-1985 floating point arithmetic result having a fraction and an exponent, comprising:

• providing an exponent logic circuit that always increments the exponent of the intermediate result;
• providing a fraction logic circuit that adjusts the fraction of the intermediate result, said fraction logic circuit further comprising a normalizer circuit that normalizes the fraction of the intermediate result, a rounder circuit that rounds the fraction of the intermediate result, and a select control circuit that selects one of a plurality of formatting procedures, where said formatting procedure selected uses the output from either said normalizer circuit or said rounder circuit to generate the result fraction in proper result mantissa in ANSI/IEEE 754-1985 format;
• and
• coupling a control logic circuit to said exponent logic circuit and to said fraction logic circuit, said control logic circuit comprises logic circuitry that controls said exponent logic circuit and said fraction logic circuit, and sets the round control bit.

A method that normalizes and rounds an ANSI/IEEE 754-1985 floating point arithmetic intermediate result having a fraction and an exponent, comprising:

• always incrementing the exponent of the intermediate result;
• normalizing the intermediate result;
• rounding the fraction of the intermediate result;
• and
• selecting one of a plurality of formatting procedures, where said formatting procedure selected uses the normalized intermediate result fraction or the rounded intermediate result fraction to generate the result fraction in ANSI/IEEE 754-1985 format.