Apparatus and method for computer system interrupt emulation

A method for emulating an interrupt, the method comprising the steps of:

• (a) receiving an interrupt request;
• (b) accessing a register of an integrated circuit through a test circuit of the integrated circuit;
• (c) saving a content of the register in a storage location;
• and
• (d) setting the register to a state responsive to the interrupt request, wherein the interrupt request is a system reset interrupt.

An apparatus for emulating an interrupt comprising:

• means for receiving an interrupt request;
• means for accessing a register of an integrated circuit through a test circuit of the integrated circuit;
• means for saving a content of the register in a storage location;
• and
• means for setting the register to a state responsive to the interrupt request, wherein said interrupt request is a system reset interrupt.

An apparatus for emulating computer system interrupts, the apparatus comprising:

• at least one JTAG-compliant integrated circuit having a test circuit with access to a register of said at least one integrated circuit;
• a processor having a test circuit interface coupled to said test circuit through a bus;
• and
• a program executable by said processor, said program, in response to an interrupt request, having said processor save a system state of said integrated circuit and set a system state of said integrated circuit, wherein said interrupt request is a system reset interrupt.

A method for emulating a system reset interrupt to a multiple processor (MP) system, said MP system comprising two or more system processors, a service processor, and a test bus coupling said two or more system processors and said service processor, said method comprising the steps of:

• executing stop code in said service processor in response to a system reset signal coupled to said service processor, said stop code operable to set a stop instruction register bit in each of said two or more system processors using test signals coupled to said two or more system processors via said test bus;
• executing interrupt code in said service processor after executing said stop code, said interrupt code operable to set a processor interrupt register bit in each of said two or more system processors using said test signals coupled to said two or more system processors via said test bus;
• executing start code in said service processor after executing said stop code and said interrupt code, said start code operable to reset said stop instruction register bit in each of said two or more system processors using said test signals coupled to said two or more system processors via said test bus;
• and
• executing in each of said two or more system processors a system reset instruction sequence when said processor interrupt register bit is set and said stop instruction bit is reset, said system reset instruction sequence executing pre-determined reset operations within each of said two or more system processors.

An apparatus for emulating a system reset interrupt to a multiple processor (MP) system, said MP system comprising two or more system processors, remote circuits, and a test bus coupling said two or more system processors and said remote circuits, said remote circuits further comprising:

• a stop circuit receiving a system reset signal, said stop circuit, in response to said remote signal, operable to set a stop instruction register bit in each of said two or more system processors using remote test signals coupled to said system processor via said test bus;
• an interrupt circuit receiving from said stop circuit a stop complete signal when said stop instruction bits are set, said interrupt circuit operable to set a processor interrupt register bit in each of said two or more system processors using said remote test signals coupled to said system processor via said test bus;
• a start circuit receiving from said interrupt circuit an interrupt complete signal when said processor interrupt register bits are set, said start circuit operable to reset said stop instruction bit in each of said two or more system processors using said remote test signals coupled to said system processor via said test bus;
• and
• system reset instruction circuits in each of said two or more system processors operable, when said processor interrupt register bit is set and said stop instruction bit is reset, to execute pre-determined reset operations within each of said two or more system processors.