Digital sliding pole fast-restore for an electrocardiograph display

A circuit for processing ECG signals, the circuit comprising:

• an amplifier for amplifying the ECG signals;
• a switch coupled to the amplifier, the switch being switchable between at least two positions, the position of the switch determining the high pass frequency response curve of the circuit, the switch being controlled by a switch control signal;
• the switch in a first position causing the circuit to have a first high pass frequency response curve with a first pole that is low enough to allow processing of ECG signals;
• the switch in a second position causing the circuit to have a second high pass frequency response curve with a second pole that is high enough to cause the amplifier of the circuit to be brought out of saturation within a specified period of time;
• a control program for providing the switch control signal, the switch control signal being a pulse waveform with an operating frequency and a duty cycle, the duty cycle being adjusted in incremental steps by the control program so as to shift the high pass frequency response of the circuit in incremental steps from the second frequency response curve to the first frequency response curve;
• and
• a QRS detect mark generator coupled to the amplifier, wherein the operating frequency of the pulse waveform is above the upper frequency of a typical ECG bandwidth as a result of which adjustments to the pulse waveform duty cycle do not cause the QRS detect mark generator to produce erroneous QRS detect marks.

A high pass filter for processing ECG signals, the high pass filter comprising:

• an output for providing the processed ECG signals;
• an amplifier coupled to the output;
• a control means for providing a pulse waveform with an adjustable duty cycle having at least a first level and a second level, the duty cycle of the pulse waveform determining the pole of the high pass frequency response curve of the high pass filter, the duty cycle at the first level adjusting the pole of the high pass filter to a frequency of approximately 0.05 Hertz, the duty cycle at the second level adjusting the pole of the high pass filter to a frequency that is greater than 0.05 Hertz;
• and
• the control means including an adjustment routine that sets the duty cycle at the second level and then adjusts the duty cycle in incremental steps so as to shift the duty cycle from the second level to the first level.

A circuit for processing ECG signals, ECG signals having a typical bandwidth with an upper frequency, the circuit comprising:

• a control circuit for providing a pulse waveform control signal with a duty cycle;
• a high pass filter with an adjustable pole coupled to the control circuit;
• an output coupled to the high pass filter for outputting processed ECG signals;
• and
• a QRS detect mark generator coupled to the output, the pole of the high pass filter being adjustable by the pulse waveform control signal that is provided by the control circuit, the pulse waveform having an operating frequency that is above the upper frequency of a typical ECG bandwidth as a result of which adjustments to the duty cycle of the pulse waveform by the control circuit do not cause the QRS detect mark generator to produce erroneous QRS detect marks at the output of the circuit.

In an ECG monitoring circuit with a high pass frequency response curve with a pole, a method for adjusting the pole of the high pass frequency response curve, the ECG monitoring circuit including an amplifier and a means for determining when the amplifier is saturated, the pole of the high pass frequency response curve being adjustable by a control circuit that produces an adjustable pulse waveform control signal with a duty cycle, the pole being at a first frequency for normal ECG monitoring when the duty cycle is at a first level and being at a second frequency for fast unsaturation of the amplifier when the duty cycle is at a second level, the method comprising:

• (a) placing the duty cycle at the first level for normal ECG signal monitoring;
• (b) determining when the amplifier is saturated;
• (c) when the amplifier is saturated, changing the duty cycle to the second level for fast unsaturation of the amplifier;
• and
• (d) returning the duty cycle from the second level to the first level in incremental steps.