Switched-current fuzzy processor for pattern recognition

A switched-current fuzzy processor, which comprises:

• means for decoding a feature input into a set of binary feature signals;
• an array of MFGs, coupled to said decoding means, for obtaining a set of current outputs whose magnitudes are proportional to the values of the feature signals respectively;
• weight-adjusting means, coupled to said MFG array, for applying a predetermined weight factor in binary form to the output currents from said MFG array;
• summing means, coupled to said weight-adjusting means, for summing up each set of currents from each column of the MFGs in said MFG array to thereby obtain a total value for the currents therefrom, wherein said summing means includes
• an array of summing circuits, each summing circuit being used to sum up the currents from the MFGs in one column of said MFG array, each summing circuit comprising:
• an input port which takes on the sequentially outputted weighted currents from said weight-adjusting means;
• transistor at least three switching MOS transistors including a first switching MOS, a second switching MOS transistor, a third switching MOS transistor;
• six NMOS transistors including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;
• and one PMOS transistor;
• wherein
• said first switching MOS transistor is connected between the input port and a first node, with the ON/OFF state thereof controlled by a first clock signal;
• said second switching MOS transistor is connected between the gate of said first NMOS transistor and a second node, with the ON/OFF state thereof also controlled by the first clock signal;
• said third switching MOS transistor is connected between the second node and both the gate of the second NMOS transistor and the gate of the third NMOS transistor, with the ON/OFF state thereof also controlled by a second clock signal which is complement to the first clock signal;
• said PMOS transistor has a gate connected to a fixed voltage, a source connected to the first node, and a drain connected to the second node;
• said first NMOS transistor has a gate connected to said second switching MOS transistor, a drain connected to the first node, and a source connected to the ground;
• said second NMOS transistor has a gate connected to both said third switching MOS transistor and the gate of said third NMOS transistor, a drain connected to the first node, and a source connected to the ground;
• said third NMOS transistor has a gate connected to the gate of said second NMOS transistor, a drain connected to a third node, and a source connected to the ground;
• said fourth NMOS transistor has a gate connected to a fourth node, a drain connected also to the fourth node, and a source connected to the ground;
• said fifth NMOS transistor has a gate connected to the fourth node, a drain connected to the source of said sixth NMOS transistor, and a source connected to the ground;
• and
• said sixth NMOS transistor has a gate connected to the enable signal, a source connected to the drain of said fifth NMOS transistor, and a drain serving as the output of said summing circuit;
• and
• a maximum-value determination circuit, coupled to said summing means, capable of obtaining the one of the currents with the maximum magnitude from said summing means.

A switched-current fuzzy processor, which comprises:

• means for decoding a feature input into a set of binary feature signals;
• an array of MFGs, coupled to said decoding means, for obtaining a set of current outputs whose magnitudes are proportional to the values of the feature signals respectively;
• weight-adjusting means, coupled to said MFG array, for applying a predetermined weight factor in binary form to the output currents from said MFG array;
• summing means, coupled to said weight-adjusting means, for summing up each set of currents from each column of the MFGs in said MFG array to thereby obtain a total value for the currents therefrom;
• and
• a maximum-value determination circuit, coupled to said summing means, capable of obtaining the one of the currents with the maximum magnitude from said summing means, wherein the maximum-value determination circuit comprises:
• a WTA circuit coupled to receive the output currents from said respective summing circuits in said summing means, said WTA circuit having a number of output ports respectively corresponding to the received currents from said summing means, wherein the one of the output ports corresponding to the one of the received currents with the maximum magnitude is at a first voltage state, with all the other output ports being at a second voltage state;
• and
• an array of non-linear conversion circuits coupled respectively to the output ports of said WTA circuit.