Synchronization in an SDH network
AssigneeMarconi Communications, Inc.
InventorSteven T Chapman
Life of this patent
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Abstract
An SDH network is enclosed in which the occurrence of closed timing loops is prevented by causing each node to stamp the clock signal passing through that node with identifying data. In one embodiment, each node is operative to overstamp any node identifying data from preceding nodes and to indicate that the timing signal is not to be used for synchronization purposes if the node to which it is being sent would result in a closed timing loop. In a second embodiment, node identifying data is added to a list, and if any node reads its own indenting data on that list, then it knows not to use the synchronization signal. By counting the number of nodes through which the signal has passed, a way is provided for preventing the occurrence of synchronization reference chains of excessive length.
Claims8
A synchronous digital hierarchy (SDH) network, comprising:
- a plurality of nodes interconnected by bi-directional links, an external clock signal being present at an input of one of said nodes, said nodes being arranged to pass the clock signal from node to node for synchronization, each node including means for stamping the clock signal passing through the respective node with data identifying that node as part of a means for preventing the occurrence of closed timing loops.
A method of preventing the occurrence of closed timing loops within an SDH network, which network comprises a plurality of nodes interconnected by bi-directional links and which are arranged to pass an external clock signal from node to node for synchronization purposes, said method comprising the step of stamping the clock signal passing through each node with data identifying that node.
Dependencies are inferred from the claim text.