ATM cell processing apparatus
AssigneeHitachi, Ltd.
InventorsKenichi Sakamoto, Akio Makimoto, Akihiko Takase, Norihiko Moriwaki, Atsushi Kiuchi
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Abstract
An ATM cell processing apparatus including a DRAM for a frame producing buffer of a frame producing unit. In order to absorb the anisotropy of the access rate of the DRAM access, the random access mode of the DRAM access is always used. To compensate a drop in access rate in this case, the DRAM is arranged is an array form and each cell is divided. Resultant partial cell data are written into and read from respective DRAM banks in order. As a result, a fast cell buffer having a large capacity can be formed. The present cell buffer can be applied to a FIFO and the like as well.
Claims16
An ATM cell processing apparatus comprising:
- a first memory formed of a plurality of banks for temporarily storing ATM cells, forming a frame received from a plurality of input lines;
- a second memory for storing frame management information to manage a state of said frame stored in said first memory for each connection;
- and
- a control unit, wherein said control unit comprises:
- a control mechanism for dividing an ATM cell into a plurality of partial cell data according to a division number based on excess capacity of said plurality of banks of said first memory, successively writing said partial cell data into respective banks of said first memory according to said frame management information stored in said second memory, and in response to arrival of said ATM cells forming one frame, successively reading parts of said frame from respective banks of said first memory to produce said frame.
An ATM cell processing apparatus, comprising:
- a first memory formed of a plurality of banks for temporarily storing ATM cells to disassemble a frame received from a plurality of input lines into ATM cells;
- a second memory for storing frame management information to manage a state of said frame stored in said first memory for each connection;
- and
- a control unit, wherein said control unit comprises:
- a control mechanism for dividing said ATM cell into a plurality of partial cell data according to a division number based on an excess capacity of said plurality of banks of said first memory, successively writing partial cell data into respective banks of said first memory according to said frame management information stored in said second memory, and in response to arrival of one frame, successively reading parts of said frame from respective banks of said first memory to produce said ATM cells.
Dependencies are inferred from the claim text.