Synchronous memory device with programmable write cycle and data write method using the same

A data write method of a synchronous memory device for writing data to a particular memory cell in response to activation of a column selection signal, the method comprising:

• programming the number of reference clock cycles required for execution of a write command, and storing the programmed data in at least one bit of a mode register set of the synchronous memory device;
• receiving a write enable signal, which changes a mode to a write mode, to generate a write master signal and a write master delay signal;
• generating an input/output line precharge signal in response to a reference clock signal and the write master delay signal, the precharge signal being disabled for the execution of the write command if the programmed number of reference clock cycles is more than one;
• generating a column selection line disable signal which is disabled in response to activation of the precharge signal;
• and
• generating a column selection signal which is enabled in response to the activation of the column selection line corresponding to a decoded address, and is disabled in response to the column selection line disable signal.