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US 6,185,142 B2Granted
Apparatus for a semiconductor memory with independent reference voltage
AssigneeSharp Kabushiki Kaisha
InventorYasuhiro Hotta
Life of this patent
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Abstract
A semiconductor memory of the present invention includes a sense amplifier for amplifying a potential difference between a potential of a first terminal and a potential of a second terminal, a first load gate located between the first terminal and a bit line, and a second load gate located between the second terminal and a reference line. A current flowing to the first load gate is controlled by a potential of the bit line, and a current flowing to the second load gate is controlled by a potential of the reference line.
Claims7
A semiconductor memory comprising:
- a sense amplifier for amplifying a potential difference between a potential of a first terminal and a potential of a second terminal;
- a first load gate connected between the first terminal and a bit line;
- and
- a second load gate connected between the second terminal and a reference line,
- wherein:
- a current flowing to the first load gate is controlled by a potential of the bit line;
- and a current flowing to the second load gate is controlled by a potential of the reference line, wherein said reference line potential is independent of said bit line potential.
4 more elements
A semiconductor memory comprising:
- a sense amplifier for amplifying a potential difference between a potential of a first terminal and a potential of a second terminal;
- a first load gate connected between the first terminal and a bit line;
- a second load gate connected between the second terminal and a reference line;
- a first transfer gate connected between a reference potential point and the first load gate;
- and
- a second transfer gate connected between the reference potential point and the second load gate,
- wherein:
- a current flowing to the first load gate is controlled by a potential of the bit line;
- and a current flowing to the second load gate is controlled by a potential of the reference line, wherein said reference line potential is independent of said bit line potential.
6 more elements
Dependencies are inferred from the claim text.