Semiconductor device allowing efficient evaluation of fast operation
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTetsushi Hoshita, Yuto Ikeda
Life of this patent
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Abstract
A precharge control circuit controls on/off of transfer gates to set a signal level of a precharge control signal in accordance with a level of a control signal input to a precharge command input pad when a write recovery test signal is active. In a normal operation, the precharge control circuit deactivates the write recovery test signal to set the signal level of the precharge control signal in accordance with a combination of control signals. Consequently, the precharge operation can be started in accordance with an arbitrary control signal generated by an external memory tester or the like in a test mode, and thereby evaluation of a write recovery time can be executed.
Claims12
A semiconductor device for operating in response to a plurality of control signals, comprising:
- a plurality of pads for receiving a plurality of control signals;
- a precharge control pad for receiving a test precharge signal for designating precharge timing in a test mode;
- a memory cell array including a plurality of memory cells arranged in rows and columns,
- said memory cell array including a plurality of bit line pairs arranged corresponding to the respective columns of said memory cells;
- and
- a control circuit for controlling operations of said semiconductor device in response to said plurality of control signals,
- said control circuit including a precharge control circuit for instructing a precharge operation for said plurality of bit line pairs, and
- said precharge control circuit instructing execution of said precharge operation in accordance with a combination of the signal levels of said plurality of control signals in a normal operation, and instructing execution of said precharge operation in accordance with the signal levels of said test precharge signal in the test mode.
A semiconductor device for operating in response to a plurality of control signals, comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns,
- said memory cell array including a plurality of bit line pairs arranged corresponding to the respective columns of said memory cells;
- and
- a control circuit for controlling operations of said semiconductor device in response to said plurality of control signals,
- said control circuit including:
- a write control circuit for activating an internal write control signal instructing a write operation for said memory cell array, and
- a precharge control circuit for instructing a precharge operation for said plurality of bit line pairs, and
- said precharge control circuit instructing execution of said precharge operation in accordance with a combination of the signal levels of said plurality of control signals in a normal operation, and instructing execution of said precharge operation after elapsing of a predetermined time from activation of said internal write control signal in a test mode.
Dependencies are inferred from the claim text.