Sensing architecture with decreased precharge voltage levels

A sensing architecture for a digital memory comprising a plurality of memory cells

• arranged in a plurality of rows and a plurality of columns:
• a plurality of read bitlines, each of the plurality of read bitlines corresponding to one of the plurality of columns;
• a bitline precharge circuit for establishing the precharge voltage at a first node on a first one of the plurality of bitlines, the bitline precharge circuit comprising:
• a first n-type transistor with a drain coupled to receive a power supply signal at voltage Vdd and a gate coupled to receive a precharge signal;
• a second n-type transistor with a drain and gate coupled to the source of the first n-type transistor, the source of the second n-type transistor coupled to the first node;
• a column select circuit comprising:
• a third n-type transistor with a drain coupled to a sense amplifier input node Vdd and a gate coupled to receive a column select signal;
• a fourth n-type transistor with a drain and gate coupled to the source of the third n-type transistor, the source of the second n-type transistor coupled to the first node;
• a sense amplifier precharge circuit comprising a p-type transistor with a source coupled to receive the power supply signal at voltage Vdd, a gate coupled to receive the inverse of the precharge control signal, and a drain coupled to the sense amplifier input node;
• wherein
• the first, second, third and fourth n-type transistors have an identical threshold voltage Vtn.