Method and apparatus for testing random access memory devices
AssigneeSTMicroelectronics S.r.l.
InventorJames Brady
Life of this patent
Estimating the term…
Abstract
A method and apparatus for testing a random access memory device, such as a dynamic random access memory device embedded within an integrated circuit chip. The apparatus includes one or more rows of transistors, each of which is connected to a bit line pair of the memory device and to a data line. Data is placed onto the bit lines by driving the data line to a predetermined voltage level and turning on the transistors in the transistor row. Data placed on the bit lines forms a test pattern that may be subsequently written into any row of memory cells. By directly controlling the bit lines of the memory device in this way, test patterns may be quickly and easily stored in the memory device for functional verification thereof.
Claims17
A method of testing a random access memory device having a memory array of memory cells, a plurality of bit lines to which a plurality of columns of memory cells in said memory array are connected, the bit lines being grouped into pairs of bit lines, a plurality of word lines to which rows of memory cells in said memory array are connected, a control line, at least one data line, and a plurality of transistors connected to said data line, each transistor being connected to a distinct bit line and having a control electrode connected to said control line, said method comprising the steps of:
- selectively driving said data line to a voltage representative of a logic level;
- driving said control line to turn on said transistors and connect said bit lines to said data line so that each bit line pair includes a bit line connected to said data line;
- driving one of said word lines to a voltage level to store data representing the voltage placed on said bit lines during said step of driving said control line, in each memory cell in a row of memory cells associated with said driven word line;
- and
- retrieving data stored in the row of memory cells.
A method of testing a random access memory device having a memory array arranged in rows and columns of memory cells, a plurality of bit lines to which a plurality of columns of memory cells in said memory array are connected, the bit lines being grouped into pairs of bit lines, a plurality of word lines to which rows of memory cells in said memory array are connected, the method comprising:
- placing at least one voltage on at least one bit line of each bit line pair so as to create a charge differential across each bit line pair, the at least one voltage representing at least one logic level;
- connecting each memory cell in a selected row of memory cells to the bit lines;
- disconnecting each memory cell in the selected row of memory cells from the bit lines;
- and
- reading the data stored in memory cells of the selected row.
A method of testing a random access memory device having a memory array arranged in rows and columns of memory cells, a plurality of bit lines to which a plurality of columns of memory cells in said memory array are connected, the bit lines being grouped into pairs of bit lines, a plurality of word lines to which rows of memory cells in said memory array are connected, the method comprising:
- creating a charge differential across each bit line pair, a polarity of each charge differential representing at least one logic level;
- connecting each memory cell in a selected row of memory cells to the bit lines;
- disconnecting each memory cell in the selected row of memory cells from the bit lines;
- and
- reading the data stored in the memory cells of the selected row.
Dependencies are inferred from the claim text.