Semiconductor memory device with decreased current consumption
AssigneeFujitsu Limited
InventorsHajime Sato, Satoru Kawamoto
Life of this patent
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Abstract
A memory device, such as a DRAM, includes multiple cell blocks, each having bit lines and word lines. Block control circuits are connected to respective ones of the cell blocks. The block control circuits supply a precharge signals to their associated cell blocks. A block control circuit which is connected to a defective cell block generates a precharge signal having a precharge level of the bit lines and a reset level of the word lines in accordance with an access condition of the defective cell block. The block control circuit sets the precharge signal to the precharge level when the defective cell block is activated and to the reset level when it is deactivated.
Claims12
A semiconductor memory device comprising:
- a plurality of cell blocks each having bit lines and word lines;
- and
- a plurality of block control circuits connected to the plurality of cell blocks, respectively, for supplying a precharge signal to the bit lines of an associated cell block, wherein the block control circuit corresponding to a defective cell block generates the precharge signal having one of a precharge level of the bit lines and a reset level of the word lines in accordance with an access condition of the defective cell block.
Dependencies are inferred from the claim text.