Flash EPROM using junction hot hole injection for erase
AssigneeAMIC Technology Corporation
InventorsVei-Han Chan, David K. Y. Liu, Kou-Su Chen
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Abstract
A novel erase mechanism using junction hot hole injection is disclosed for flash memory cell sector and bulk erase operations. A constant current supply is used so that a suitable junction voltage breakdown can be provided despite expected variations in cell structures, operations, etc. The inventive method eliminates the need for dual polarity voltage supplies for erase operations, and provides a method to achieve a tight distribution of erased cell threshold voltages. In addition, over-erasure problems associated with Fowler-Nordheim tunneling are essentially eliminated.
Claims41
A method of erasing a memory cell in a flash memory cell array, which cell includes a control gate, a floating gate, a source, a drain, a channel region between the source and drain, and a gate dielectric situated between the floating gate and the channel and an associated substrate, the method including the steps of:
- (a) applying a positive erase voltage to either the source or drain of such cell, said erase voltage being generated from a constant current applied to said source or drain so that a voltage is automatically adjusted in a junction of said cell to a value suitable for causing breakdown in such junction;
- and
- (b) floating the source or drain of such cell which is not already biased with said positive erase voltage;
- (c) grounding the substrate;
- (d) wherein said positive voltage is selected to be sufficient to cause positive charge carriers in the form of hot holes to move into the floating gate to erase the cell.
An integrated circuit comprising:
- an array of flash memory cells, each of said cells having a conduction threshold voltage, a control gate, a floating gate, a source and a drain;
- and
- peripheral support circuitry coupled to such array, including a constant current source generator capable of generating a current I;
- and
- a control circuit coupled to said array and said peripheral support circuitry for reducing the threshold voltages of the cells to a single target erase value, the control circuit being configured such that:
- (a) said constant current source generator can be activated so that a positive erase voltage can be applied to either the source or drain of such cells, said positive erase voltage having a value that is adjusted to a junction breakdown voltage suitable for each of said cells;
- and
- (b) whichever of the source or drain of such cells which is not already biased with said positive erase voltage is put into a floating state by said control circuit;
- wherein said current I is selected so that said positive erase voltage is sufficient to cause positive charge carriers in the form of hot holes to move into the floating gate to change each of said threshold voltages for each of said cells to said targed erase value without over-erasing any of such cells.
A method of making a flash memory integrated circuit, said method including the steps of:
- (a) providing an array of flash memory cells in said integrated circuit, each of said cells having a conduction threshold voltage, a control gate, a floating gate, a source and a drain;
- and
- (b) providing peripheral support circuitry in said integrated circuit for such array, including a constant current source generator capable of generating a current I;
- and
- (c) providing a control circuit coupled to said array and said peripheral support circuitry for reducing the threshold voltages of the cells to a single target erase value, the control circuit being configured such that:
- i) said constant current source generator can be activated so that a positive erase voltage can be applied to either the source or drain of such cells, said positive erase voltage having a value that is adjusted to achieve a junction breakdown voltage suitable for each of said cells;
- and
- ii) whichever of the source or drain of such cells which is not already biased with said positive erase voltage is put into a floating state by said control circuit;
- wherein said current I is selected so that said positive erase voltage is sufficient to cause positive charge carriers in the form of hot holes to move into the floating gate during an erase operation to change each of said threshold voltages for each of said cells to said targeted erase value without over-erasing any of such cells.
A circuit for erasing cells in a flash memory cell array, said circuit including:
- a current source generator capable of generating a substantially constant current I;
- a control circuit for applying said constant current to the cells in said array, such that a positive erase voltage signal is effectively applied to a bit line of such array, said bit line being coupled to a source or drain region of said cells, said positive erase voltage being automatically adjusted by said constant current to have a voltage value suitable for causing breakdown in a junction of said cells;
- and
- further wherein said control circuit applies a floating voltage to whichever of the source or drain of such cells is not already biased with said positive erase voltage;
- wherein said current I is selected so that said positive erase voltage is sufficient to cause positive charge carriers to move into the floating gate during an erase operation to change each of said threshold voltages for each of said cells to said targeted erase value without over-erasing any of such cells;
- and
- said control circuit being further configured such that said erase operation is effectuated substantially without using Fowler-Nordheim tunnelling.
A method of reducing negative charge stored in a flash memory cell, which cell includes a control gate, a floating gate, a source, and a drain, the method including the steps of:
- (a) applying a single positive voltage signal to either the source or drain of such cell to cause an avalanche condition in a junction associated with such source or drain so that positive charge carriers are generated, said avalanche condition being caused by a breakdown voltage that is adjusted for said cell by a constant current source;
- and
- (b) floating the source or drain of such cell which is not already biased with said positive voltage;
- (c) causing said positive charge carriers to move into the floating gate to reduce the negative charge of the cell;
- wherein said negative charge is reduced substantially without using Fowler-Nordheim tunnelling.
Dependencies are inferred from the claim text.