Sensing current reduction device for semiconductor memory device and method therefor
AssigneeHyundai Electronics Industries Co., Ltd.
InventorIn Chul Jung
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Abstract
The present invention relates to a sensing current reduction device for a semiconductor memory device, and a method therefor, which can considerably reduce a sensing current occupying a great part of an operating current and consume less power, by controlling a bit line sense amplifier to be operated after receiving a column address, and control a long-time operation not to be carried out after applying the row address. Accordingly, a time from latching a row address signal to receiving a column address signal is sharply decreased. As a result, an access time is reduced, thus achieving the high speed operation.
Claims9
A sensing current reduction device for a semiconductor memory device, comprising:
- a memory cell array consisting of a plurality of sub-cell arrays;
- a first decoder means for decoding a plurality of row address signals, and outputting a global word line selection signal;
- a second decoder means for decoding a plurality of column address signals, and outputting a global column line selection signal;
- a selection means for receiving the plurality of row address signals and the plurality of column address signals, and outputting a sub-cell array selection signal in order to select one of the plurality of sub-cell arrays;
- a third decoder means for outputting a signal enabling the sub-cell array according to the sub-cell array selection signal and the global word line selection signal;
- and
- a sense amplifier means for sensing/amplifying and outputting a data according to the sub-cell array selection signal and the global column line selection signal.
A sensing current reduction method for a semiconductor memory device, comprising the steps of:
- outputting a global word line selection signal through a plurality of row address signals;
- outputting a global column line selection signal through a plurality of column address signals;
- outputting a selection signal enabling one of a plurality of sub-cell arrays of a memory cell array through the plurality of row address signals and the plurality of column address signals, and simultaneously outputting a signal operating a sense amplifier means by delaying the selection signal for a predetermined time;
- and
- externally outputting the data by the sense amplifier means according to the global column line selection signal.
Dependencies are inferred from the claim text.