Nonvolatile semiconductor storage device capable of electrically isolating dummy cell array region from memory cell array region
AssigneeSharp Kabushiki Kaisha
InventorShuichiro Kouchi
Life of this patent
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AssigneeSharp Kabushiki Kaisha
InventorShuichiro Kouchi
Estimating the term…
A virtual-grounding memory cell array region and a virtual-grounding dummy cell array region are electrically isolated from each other while any increase in chip size is suppressed. An erase voltage Vers (−8 V) is applied to a dummy main bit line DMBL0 in a dummy cell array region 20 via an erase voltage supply transistor 2. A negative voltage (−8 V) is applied to drains of dummy cells DCELL0, DCELL0, . . . as well as sources of dummy cells DCELL1, DCELL1, . . . within a BLOCKn through dummy sub-bit lines DSBL. By electrons being injected into the floating gates of all the dummy cells DCELL in the columns of the dummy cells DCELL0 and DCELL1 within the BLOCKn, the threshold of those dummy cells DCELL becomes high. Occurrence of any charging currents and leak currents from the virtual-grounding memory cell array region to the floating capacitance of the dummy cells is prevented.
A nonvolatile semiconductor storage device comprising:
Dependencies are inferred from the claim text.