Power reset circuit of a flash memory device

Abstract

There is disclosed a power reset circuit of a flash memory device, which is characterized in that it comprises a first bootstrap circuit for raising the voltage level of a first node into a higher level upon a power-up; a latch means for inverting the voltage level of said first node; a voltage detector operable depending on the output of said latch means, for outputting a low level or a high level of signal depending on the level of the supply voltage; a second bootstrap circuit for raising the voltage level of a second node into a high level upon a power-up; a delay means for delaying and outputting the voltage level of said second node, a transfer means operable depending on the output of said delay means, for transferring the output of said voltage detector; and a feedback means for feedbacking the output of said voltage detector to said first node and said second node.

Dependencies are inferred from the claim text.