Circuit for measuring the data retention time of a dynamic random-access memory cell

A circuit for measuring a retention time of a memory cell of a dynamic random access memory (DRAM), the circuit comprising:

• a DRAM memory cell, the DRAM memory cell comprising an N-type metal-oxide semiconductor (NMOS) transistor and a capacitor, where a source region of the NMOS transistor is coupled to a lower end of the capacitor, a drain region of the NMOS transistor is coupled to a first voltage, a gate electrode of the NMOS transistor is coupled to a second voltage, and a third voltage is applied onto an upper end of the capacitor, wherein there is a node between the NMOS transistor and the capacitor;
• a first periphery metal-oxide semiconductor (MOS) device, wherein a gate electrode of the first periphery MOS device is coupled to the node used for receiving a voltage existing at the node, a drain region of the first periphery MOS device is coupled to a fourth voltage, and a source region of the first periphery MOS device is coupled to a fifth voltage;
• and
• a second periphery MOS device, which is coupled with the first periphery MOS device in parallel, but a gate electrode of the second periphery MOS device is coupled to a sixth voltage.