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US 6,185,123 B2Granted
Memory cell configuration for a 1T/1C ferroelectric memory
AssigneeRamtron International Corporation
InventorsJudith E. Allen, William F. Kraus, Lark E. Lehman
Life of this patent
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Abstract
A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.
Claims1
A memory cell comprising:
- a transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node;
- a shunt word line extending across the memory cell that is electrically isolated from the word line and the transistor within the physical boundary of the memory cell;
- and
- a capacitor coupled to the internal cell node.
1 more element
Dependencies are inferred from the claim text.