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US 6,185,122 B2Granted
Vertically stacked field programmable nonvolatile memory and method of fabrication
AssigneeMatrix Semiconductor, Inc.
InventorsMark G. Johnson, Thomas H. Lee, Vivek Subramanian, P. Michael Farmwald, James M. Cleeves
Life of this patent
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Abstract
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
Claims59
A memory array comprising:
- a first plurality of spaced-apart, parallel, substantially coplanar conductors;
- a second plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the first conductors, said first and second conductors being generally orthogonal to one another;
- and
- a plurality of first memory cells each comprising a first steering element in contact with a first state change element, each cell directly disposed between one of the first and one of the second conductors and located where a vertical projection of the first conductors intersects the second conductors, the first steering elements being in contact with the second conductors;
- a third plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the second conductors, the third conductors running in the same direction as the first conductors;
- a plurality of second memory cells each comprising a second steering element in contact with a second state change element, each cell directly disposed between one of the second conductors and one of the third conductors and located where a vertical projection of the second conductors intersects the third conductors, the second steering elements being in contact with the second conductors.
3 more elements
A memory array comprising:
- a plurality of conductors on levels 1, 2, 3, 4 . . . where the levels are parallel and spaced-apart, the conductors in the odd numbered levels 1, 3 . . . running in a first direction, the levels in the even numbered levels 2, 4 . . . running in a second direction, generally perpendicular to a first direction, and
- a plurality of memory cells each having an input terminal directly connected to a diode and an output terminal with a state change element directly connected between the diode and the output terminal, the cells being disposed between conductors in each of the levels 1, 2, 3, 4 . . . ;
- the input terminals of the cells being directly connected to the conductors in the odd numbered levels 1, 3 . . . and the output terminals of the cells being directly connected to the conductors in the even numbered levels 2, 4 . . . .
A process for fabricating a memory array comprising:
- (a) forming a first layer of conductive material;
- (b) forming a plurality of second layers for defining memory cells on the first layer;
- (c) patterning the second layers into a plurality of parallel, spaced-apart strips;
- (d) etching the first layer in alignment with the strips formed from the second layers;
- (e) forming insulating material between the strips of first layer material and the strips formed from the second layers;
- (f) forming a third layer of conductive material on the insulating material and the strips formed from the second layer;
- (g) forming a plurality of fourth layers for defining memory cells of the second level;
- (h) patterning the fourth layers into a plurality of parallel, spaced-apart strips, the strips formed from the fourth layers running generally perpendicular to the strips formed from the first layer;
- (i) etching the third layer and the strips formed from the second layers in alignment with the strips formed from the fourth layers.
6 more elements
A memory array comprising:
- a plurality of conductors on levels 1, 2, 3, 4 . . . where the levels are parallel and spaced-apart, the conductors in the odd numbered levels 1,3 . . . running in a first direction, the levels in the even numbered levels 2,4 . . . running in a second direction, generally perpendicular to a first direction, and
- a plurality of memory cells each having an input terminal directly connected to a diode terminal with a state change element directly connected between the diode and the output terminal;
- wherein the output terminal of the cells are connected to the conductors in the odd numbered levels 1, 3 . . . and the input terminal of the cells are connected to the conductors in the even numbered levels 2, 4 . . . .
A memory comprising:
- a memory array having:
- a first plurality of spaced-apart, parallel, substantially coplanar conductors;
- a second plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the first conductors, said first and second conductors being generally orthogonal to one another;
- a plurality of first memory cells, each cell disposed between one of the first and one of the second conductors and located where a vertical projection of the first conductors intersects the second conductors;
- a third plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the second conductors, the third conductors running in the same direction as the first conductors;
- a plurality of second memory cells, each cell disposed between one of the second conductors and one of the third conductors and located where a vertical projection of the second conductors intersects the third conductors, and
- a semiconductor substrate on which the array is formed, the substrate containing circuitry for communicating with the first and second memory cells, the circuitry being coupled to the first, second and third plurality of conductors.
4 more elements
Dependencies are inferred from the claim text.