Analog memory IC with fully differential signal path
AssigneeSanDisk Corporation
InventorsAndreas M. Haeberli, Carl W. Werner, Hock C. So, Sau C. Wong, Cheng-Yuan Michael Wang, Leon Sea Jiunn Wong
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Abstract
An integrated circuit memory is capable of storing analog information without the need for A/D conversion. Samples of a analog signal input are stored in nonvolatile memory cells. The integrated circuit is also capable of storing digital information in digital form. The sampling rate at which the analog signal input is sampled is user selectable. An internal signal path of the integrated circuit memory is differential, which enhances the precision with which the analog signal is stored in the memory cells.
Claims31
An integrated circuit comprising:
- an analog data differential input;
- a preamplifier circuit coupled to amplify an analog signal at the analog data differential input with a first gain, wherein an amplified output signal is provided at a first differential output;
- a low pass filter circuit coupled to the preamplifier differential output, wherein the low pass filter circuit provides samples of the analog signal at a second differential output;
- a first level shifter circuit coupled to the second differential output, wherein the first level shifter circuit performs a sample and hold operation, an amplification, and a voltage shift, which results in a first level shifter output signal at a first offset voltage above a level of a sample at the second differential output;
- and
- an array of analog memory cells, wherein the first level shifter output is coupled to the array of memory cells.
An integrated circuit comprising:
- an array of analog memory cells;
- a ramp circuit coupled to a memory cell of the array, wherein the ramp circuit determines a stored threshold voltage of the memory cell;
- and
- a playback level shifter coupled to a ramp output of the ramp circuit, wherein the playback level shifter provides a first differential output coupled to an output of the integrated circuit.
An integrated circuit comprising:
- a preamplifier circuit;
- a low pass filter circuit coupled to the preamplifier circuit;
- a first level shifter coupled to the low pass filter;
- a second level shifter coupled to the low pass filter;
- an array of memory cells coupled to the first and second level shifters;
- a master bias generator generating a master bias voltage;
- and
- a plurality of slave bias generators, each coupled to the master bias voltage, wherein a first slave bias generator is coupled to the preamplifier circuit, a second slave bias generator is coupled to the first and second level shifters, and the slave bias generators each have an enable input.
Dependencies are inferred from the claim text.