A liquid crystal display apparatus comprising:
- a substrate;
- gate wires and source wires formed in a matrix on said substrates;
- gate electrodes formed in proximity to points of intersection between said gate wires and source wires, said gate electrodes being connected electrically to said gate wires;
- a first insulating film formed on said gate wires and said gate electrodes, said first insulating film further carrying said source wires thereon;
- a semiconductor active film formed over said gate electrodes with said first insulating film interposed therebetween;
- source electrodes formed on said semiconductor active film and connected with said source wires;
- drain electrodes formed on said semiconductor active film and isolated from said source electrodes;
- an electrode film formed on said first insulating film, said electrode film being proximate to and in parallel with said source wires, said electrode film generating capacitance;
- a second insulating film formed on said first insulating film, said first insulating film carrying said electrode film, said source wires, said source electrodes, said drain electrodes and said semiconductor active film thereon;
- and
- pixel electrodes connected to said drain electrodes and formed on said second insulating film, said pixel electrodes generating capacitance in cooperation with said electrode film;
- wherein said pixel electrode has a first end and a second end, said electrode film is disposed at said first end of said pixel electrode, said gate electrode, said source electrode, and said drain electrode are disposed at said second end of said pixel electrode to drive said pixel electrode;
- a first contact hole is formed in both said first insulating film and said second insulating film to a longitudinal portion of the gate wiring located adjacent to and corresponding with said pixel electrode;
- a second contact hole is formed in said second insulating film to said electrode film;
- and
- a connecting path electrically connecting said electrode film and the gate wiring adjacent to said pixel electrode via said first and second contact holes is formed simultaneously with forming said pixel electrode.