Method and apparatus for split shift register addressing

Abstract

An addressing circuit designed for implementation within the device being addressed that uses less silicon space by selecting the desired address with shift register outputs. A fast shift register is coupled to a slow shift register by a combinatorial circuit having inputs from the fast shift register and the slow shift register to providing the selected address. A timing circuit is electrically coupled to each the fast shift register and the slow shift register. A mode select circuit that is operatively coupled to at least one of either the fast shift register or the slow shift register. The mode select circuit comprises a Boolean logic circuit that is operatively coupled to at least one of either the slow shift register or the fast shift register, the Boolean logic circuit having at least one logical input that determine a first portion of at least one of the shift registers to be used and a second portion of at least one of the shift registers to be discarded.

Dependencies are inferred from the claim text.