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US 6,184,907 B2Granted
Graphics subsystem for a digital computer system
AssigneeSamsung Electronics Co., Ltd.
InventorByung-Gueon Min
Life of this patent
Estimating the term…
Abstract
A graphics subsystem utilizes a single port DRAM as a frame buffer, which has an r-bit wide data access port and stores video data that are generated by an application program executed on a host processor. The graphics subsystem includes a first-in first-out (FIFO) buffer for storing the video data from the frame buffer, and a scan interpolator for performing vertical and horizontal interpolation of data read from the FIFO buffer with respect to a predetermined number of adjacent scan lines on a video frame. By interpolating adjacent scan lines in real time, it is possible to obtain high-quality images on a computer or television display.
Claims25
A graphics system for processing data generated by a host processor and for providing said data to a display device comprising:
- a first frame buffer having an r-bit wide data access port, where r is a positive integer, for storing video data generated by an application program executed on said host processor;
- a second buffer comprising:
- a RAM array for periodic storage of a portion of the video data stored in said frame buffer, and for periodic transmission of scan line data to said display device, said second buffer generating a read request control signal when at least one storage location therein is vacant;
- a control logic for generating a read strobe control signal and a mode select control signal in response to a display control signal from said display device from said display device;
- first and second address pointers for generating first and second read addresses respectively in response to the read strobe control signal;
- and
- an address selector for selecting one of the first and second read addresses and providing the selected address to said RAM array in response to the mode select control signal;
- a controller for controlling read and write operations of said frame buffer and said second buffer in response to the read request control signal from said second buffer;
- and
- a scan interpolator for vertically interpolating said scan line data transmitted from said second buffer, with respect to a predetermined number of scan lines on the display device.
7 more elements
A graphics system for processing data generated by a host processor and for providing said data to a display device comprising:
- a first frame buffer having an r-bit wide data access port, where r is a positive integer, for storing video data generated by an application program executed on said host processor;
- a second buffer for periodic storage of a portion of the video data stored in said frame buffer, and for periodic transmission of scan line data to said display device, said second buffer generating a read request control signal when at least one storage location therein is vacant;
- said second buffer comprising:
- a RAM array including first and second storage regions which have identical storage capacity, for storing the video data provided from said frame buffer;
- a control logic for generating a write strobe control signal, a read strobe control signal and a mode select control signal in response to a display control signal from said display controller, a write enable control signal from a memory controller and a host command issued from said host processor, respectively;
- a first address pointer for generating a write address in response to the write strobe control signal, the write address being used to write the video data provided from said frame buffer into said RAM array;
- a second address pointer for generating a first read address in response to the read strobe control signal, the first read address being used to read the video data stored in said RAM array successively;
- a third address pointer for generating a second read address in response to the read strobe control signal, the second read address being used to read the video data stored in said RAM array discretely;
- and
- an address selector for selecting one of the first and second read addresses and providing the selected address to said RAM array, in response to the mode select control signal;
- a controller for controlling read and write operations of said frame buffer and said second buffer in response to the read request control signal from said second buffer;
- and
- a scan interpolator for vertically interpolating said scan line data transmitted from said second buffer, with respect to a predetermined number of scan lines on the display device.
10 more elements
A graphics system for processing data generated by a host processor and for providing said data to a display device comprising:
- a first frame buffer having an r-bit wide data access port, where r is a positive integer, for storing video data generated by an application program executed on said host processor;
- a second buffer for periodic storage of a portion of the video data stored in said frame buffer, and for periodic transmission of scan line data to said display device, said second buffer generating a read request control signal when at least one storage location therein is vacant;
- a controller for controlling read and write operations of said frame buffer and said second buffer in response to the read request control signal from said second buffer;
- and
- a scan interpolator for vertically interpolating said scan line data transmitted from said second buffer, with respect to a predetermined number of scan lines on the display device, wherein said scan interpolator comprises:
- a first register for storing a first pixel data provided from said second buffer and associated with the (i−1)-th scan line (SLi−1);
- a second register for storing a second pixel data provided from said second buffer and associated with the i-th scan line (SLi);
- a register controller for controlling read and write operations of said first and second registers, said register controller instructing said first and second registers to output their stored data when a third pixel data associated with the (i+1)-th scan line (SLi+1) is provided from said FIFO buffer;
- a first divider for dividing an output of said first register by a first interpolation coefficient;
- a second divider for dividing an output of said second register by a second interpolation coefficient;
- a third divider for dividing third pixel data associated with the (i+1)-th scan line (SLi+1) by a third interpolation coefficient;
- and
- an adder for adding outputs of said first to third dividers together.
10 more elements
A graphics system for processing data generated by a host processor and for providing said data to a display device comprising:
- a first frame buffer having an r-bit wide data access port, where r is a positive integer, for storing video data generated by an application program executed on said host processor;
- a second buffer for periodic storage of a portion of the video data stored in said frame buffer, and for periodic transmission of scan line data to said display device, said second buffer generating a read request control signal when at least one storage location therein is vacant;
- a controller for controlling read and write operations of said frame buffer and said second buffer in response to the read request control signal from said second buffer;
- and
- a scan interpolator for vertically interpolating said scan line data transmitted from said second buffer, with respect to a predetermined number of scan lines on the display device, wherein said scan interpolator comprises:
- a first register for storing a first pixel data provided from said second buffer and associated with the (i−1)-th scan line (SLi−1);
- a second register for storing a second pixel data provided from said second buffer and associated with the i-th scan line (SLi);
- a first divider for dividing an output of said first register by a first interpolation coefficient;
- a second divider for dividing an output of said second register by a second interpolation coefficient;
- a third divider for dividing third pixel data associated with the (i+1)-th scan line (SLi+1) by a third interpolation coefficient;
- a first adder for summing the outputs of the first, second, and third dividers;
- a third register for storing a first output of said first adder;
- a fourth register for storing a second output of said first adder;
- a fifth register for storing a third output of said first adder;
- a register controller for controlling read and write operations of said first to fifth registers, said register controller instructing said first and second registers to output their stored data when a third pixel data associated with the (i+1)-th scan line (SLi+1) is provided from said second buffer;
- a fourth divider for dividing an output of said third register by a fourth interpolation coefficient;
- a fifth divider for dividing an output of said fourth register by a fifth interpolation coefficient;
- a sixth divider for dividing an output of said fifth register by a sixth interpolation coefficient;
- and
- a second adder for summing the outputs of the fourth, fifth, and sixth dividers.
17 more elements
Dependencies are inferred from the claim text.