Multiple pipeline memory controller for servicing real time data
AssigneeATI Technologies, Inc.
InventorsChun Wang, Raymond Li, Adrian Hartog, Daniel Gudmundson
Life of this patent
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Abstract
A multiple pipeline memory controller has a plurality of two stage pipeline processors dedicated to separately process real time video capture and display refresh input request signals. A separate pipeline processor processes non-real time input signals. The multiple pipeline design reduces memory access latency and improves throughput of data in display FIFO memory to effect improved resolution. The multiple pipeline memory controller can be integrated in a video graphics controller (VGC).
Claims21
A memory controller for servicing real time data comprising:
- at least a first input port for receiving a real time request signal in a pipeline fashion;
- at least a second input port for receiving a non-real time request signal in a pipe line fashion;
- first pipeline processor, operatively coupled to the first input port, to separately process the real time request signal in a pipeline fashion wherein the first pipeline processor is a dual stage pipeline processor with a first stage addressing unit having addressing logic with first memory row/column address determination logic and first memory page fault detection logic;
- second pipeline processor, operatively coupled to the second input port, to separately process the non-real time request signal in a pipeline fashion;
- and
- wherein the first and second pipeline processors include an arbitrator to selectively determine which of the real time and non-real time request signals is to be output to memory.
A memory controller for servicing real time data comprising:
- at least a first and second input port for receiving first and second real time input signals in a pipeline fashion;
- a plurality of input ports for receiving a plurality of non-real time input signals in a pipeline fashion;
- first pipeline processor, operatively coupled to the first input port, to separately process the real time request signal in a pipeline fashion;
- second pipeline processor, operatively coupled to the second input port, to separately process the non-real time request signal in a pipeline fashion;
- first priority based arbitration logic, connected to receive the plurality of non-real time input signals from the plurality of input ports, for selecting one of the non-real time input signals based on a priority determination and outputting a selected non-real time input signal;
- third pipeline processor, operatively coupled to receive the selected non-real time input signal from the priority based arbitration logic, to separately process the selected non-real time input signal in a pipeline fashion;
- and
- wherein the first, second and third pipeline processors include second priority based arbitration logic as a final stage for selectively determining which of the real time and non-real time input signals is to be output to memory.
Dependencies are inferred from the claim text.