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US 6,184,875 B2Granted
Display apparatus
AssigneeCanon Kabushiki Kaisha
InventorMakoto Matsuura
Life of this patent
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AssigneeCanon Kabushiki Kaisha
InventorMakoto Matsuura
Estimating the term…
A display apparatus includes a CPU, an image display device, a light source for irradiating the image display device, a circuit for turning on/off the light source, a means for determining the resolution of the input image signal, a first switching means for turning on/off the power supply to the circuit components except the light source turning on/off circuit and a second switching means for turning on/off the power supply to the light source turning on/off circuit. In a first power-saving mode, the circuits may be opened by means of the first switching means after an appropriately selectable first predetermined period of time and may be opened by means of the second switching means after an appropriately selectable second predetermined period of time. A second power-saving mode is also provided for opening the first and second switching means by a combination of the polarity of the input horizontal synchronizing signal and that of the input vertical synchronizing signal. The first power-saving mode and the second power-saving mode may be used selectively.
A display apparatus comprising a CPU, an image display device, a light source for irradiating the image display device, a circuit for turning on/off the light source, a means for determining the resolution of the input image signal, a first switching means for turning on/off the power supply to the circuit components except the light source turning on/off circuit and a second switching means for turning on/off the power supply to the light source turning on/off circuit and adapted to operate in a first power-saving mode for opening the circuits by means of said first switching means after an appropriately selectable first predetermined period of time and also open the circuits by means of said second switching means after an appropriately selectable second predetermined period of time or in a second power-saving mode for opening said first and second switching means by a combination of the polarity of the input horizontal synchronizing signal and that of the input vertical synchronizing signal, said first power-saving mode and said second power-saving mode being able to be selectively used.
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Power saving in peripheral device: power saving in display device
Means for saving power: power management, i.e. event-based initiation of a power-saving mode
Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection…:…
Power management, e.g. power saving: in absence of operation, e.g. no data being entered during a predetermined time
Term ended 12 Nov 2018 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
This invention relates to a display apparatus designed to operate in a power-saving fashion that is adapted to the input image signal.
2. Related Background Art
FIG. 1 is a schematic block diagram of an embodiment of the invention.
FIG. 2 is a flow chart for the operation of the embodiment in a first power-saving mode.
FIG. 3 is a flow chart for the operation of the embodiment in a second power-saving mode.
Now, the present invention will be described in greater detail by referring to the accompanying drawings that illustrate preferred embodiments of the invention.
FIG. 1 is a schematic block diagram of an embodiment of display apparatus according to the invention and comprising an image display device adapted to selectively display image signals with different resolutions including image signals from personal computers (hereinafter referred to as PC signals) and NTSC television signals (hereinafter referred to as TV signals).
Referring to FIG. 1, there are shown a synchronization switching circuit 5 for selecting either PC synchronizing signals or NTSC synchronizing signals, a switching control circuit 15 operated by CPU 16, an NTSC vertical synchronizing signal 1, an NTSC horizontal synchronizing signal 2, a PC vertical synchronizing signal 3, a PC horizontal synchronizing signal 4, a horizontal synchronizing signal 6 and a vertical synchronizing signal 7 selected by the synchronization switching circuit 5 and an absence of signal determining circuit 8 for determining if there are no horizontal synchronizing signal 6 nor vertical synchronizing signal 7 and also if the input image signal has a frequency out of the frequency range with which the image display device is adapted to display images (hereinafter referred to signal absence). The signal absence circuit 8 also determines the polarity of each synchronizing signal.