Method and apparatus for eliminating clock jitter in continuous-time Delta-Sigma analog-to-digital converters

A continuous-time, Delta-Sigma, analog-to-digital converter for generating a digital signal, D as a function of an analog signal, U, wherein the converter receives a clock signal having a first and a second phase, and wherein the converter has a ground, the converter comprising:

• a) a loop filter receiving the analog signal U and an analog feedback signal V and generating an analog difference signal Y where the difference signal Y is equal to the difference between the analog signal U and the analog feedback signal V;
• and
• b) a quantizer receiving the analog difference signal Y and generating the digital signal D as a function of the analog difference signal Y, the quantizer including:
• i) a capacitor coupled to the ground;
• ii) a first two-position switch coupled to the capacitor, the first switch receiving an analog reference signal that is generated as a function of the digital signal and wherein the capacitor is charged with the analog reference signal during the first phase of the clock signal;
• and
• iii) a second two-position switch coupled to the capacitor, the second switch generating the analog feedback signal V by coupling the capacitor to the loop filter and generating a discharge path for the capacitor during the second phase of the clock signal;
• wherein the first phase and second phase of the clock are each long enough to ensure that minor variations in the clock cycle have a minimal effect on the integral of a voltage across the capacitor taken over the second phase of the clock.

A method for generating a digital signal, D as a function of an analog signal, U and a clock signal having a first and a second phase, the method comprising the steps of:

• a) receiving the analog signal U and an analog feedback signal V and generating an analog difference signal Y where the difference signal Y is equal to the difference between the analog signal U and the analog feedback signal V;
• b) receiving the analog difference signal Y and generating the digital signal D as a function of the analog difference signal Y;
• c) generating an analog reference signal as a function of the digital signal D;
• d) charging a capacitor with the analog reference signal during the first phase of the clock signal;
• and
• e) generating the analog feedback signal V by discharging the capacitor during the second phase of the clock signal such that the capacitor is essentially fully charged before the end of each first clock phase and essentially fully discharged prior to the end of each second clock phase, making the integral of the analog signal V over the second phase of the clock constant for each cycle of the clock.

A digital-to-analog converter for generating an analog signal V as a function of a received digital signal D, the converter receiving a clock signal having a first and a second phase, the converter comprising:

• a) means for generating an analog reference signal as a function of the digital signal D;
• b) means for charging a capacitor with the analog reference signal during the first phase of the clock signal;
• and
• c) means for generating the analog signal V by discharging the capacitor during the second phase of the clock signal such that the capacitor is essentially fully charged before the end of each first clock phase and essentially fully discharged prior to the end of each second clock phase, making the integral of the analog signal V over the second phase of the clock constant for each cycle of the clock.

A continuous-time, Delta-Sigma, analog-to-digital converter for generating a digital signal, D as a function of an analog signal, U, the converter receiving a clock signal having a first and a second phase, the converter comprising:

• a) means for receiving the analog signal U and an analog feedback signal V and generating an analog difference signal Y where the difference signal Y is equal to the difference between the analog signal U and the analog feedback signal V;
• b) means for receiving the analog difference signal Y and generating the digital signal D as a function of the analog difference signal Y;
• c) means for generating an analog reference signal as a function of the digital signal D;
• d) means for charging a capacitor with the analog reference signal during the first phase of the clock signal;
• and
• e) means for generating the analog feedback signal V by discharging the capacitor during the second phase of the clock signal.