Glitch-free bi-phased encoder
AssigneeLucent Technologies Inc.
InventorsTony S. El-Kik, Dennis A. Brooks, Richard Muscavage
Life of this patent
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Abstract
An encoder which includes a flip-flop; a first, second and third NAND gate; a first and second inverter; and a first and second delay cell. The first inverter couples the flip-flop with the first NAND gate. The first delay cell couples the first NAND gate with the third NAND gate. The second inverter couples the second delay cell with the second NAND gate. Further, the second NAND gate couples the second inverter with the third NAND gate. The third NAND gate of the encoder produces a glitch-free encoded signal.
Claims12
A circuit comprising:
- a flip-flop, the flip-flop receiving an input signal and a clock signal having clock information;
- a first, second and third gate;
- a first delay cell, the first delay cell allowing an output signal of the second gate to transition between a high and low state prior to providing a signal to the third gate;
- a second delay cell, the second delay cell allowing an output signal of the flip-flop to transition between a low and high state prior to providing the second gate with the clock signal;
- the first gate coupling the flip-flop with the first delay cell;
- the first delay cell coupling the first gate with the third gate;
- and
- the second gate coupling the second delay cell with the third gate;
- wherein the third gate provides an output signal including data and the clock information.
A Data Access Arrangement codec interface system including a transmitter codec communication with a receiver codec, the transmitter codec comprising:
- a flip-flop, the flip-flop receiving an input signal and a clock signal having clock information;
- a first, second and third gate;
- a first delay cell, the first delay cell allowing an output signal of the second gate to transition between a high and low state prior to providing a signal to the third gate;
- a second delay cell, the second delay cell allowing an output signal of the flip-flop to transition between a low and high state prior to providing the second gate with the clock signal;
- the first gate coupling the flip-flop with the first delay cell;
- the first delay cell coupling the first gate with the third gate;
- and
- the second gate coupling the second delay cell with the third gate;
- wherein the third gate provides a glitch-free output signal including data and the clock information to the receiver codec.
Dependencies are inferred from the claim text.