Clock delay circuitry producing clock delays less than the shortest delay element

Oscillation circuitry comprising:

• a delay loop into which a clock signal furnished by itself is fed back, said delay loop including a clock delay circuit provided with a plurality of delay elements each for delaying either a signal associated with the clock signal fed back into said delay loop or the clock signal fed back into said delay loop by a specified time delay which differs from other time delays provided by the others of said plurality of delay elements so as to generate a delayed clock signal, and a selector for selecting one delayed clock signal from among the plurality of delayed clock signals from said plurality of delay elements, the plurality of time delays provided by said plurality of delay elements being set such that a time lag between any two successive delayed clock signals generated by said plurality of delay elements is less than the shortest one of the plurality of time delays provided by said plurality of delay elements;
• a phase comparator for comparing the phase of a signal associated with an output of said delay loop with that of a reference clock signal applied thereto so as to generate a phase difference clock signal indicating the phase difference between them;
• and
• a delay setting circuit for causing said selector to change a selection of one delayed clock signal according to the phase difference signal from said phase comparator in such a manner as to reduce the phase difference.

Phase synchronous circuitry comprising:

• delay means including a clock delay circuit provided with a plurality of delay elements each for delaying an identical clock signal applied thereto by a specified time delay which differs from other time delays provided by the others of said plurality of delay elements so as to generate a delayed clock signal, and a selector for selecting one delayed clock signal from among the plurality of delayed clock signals generated by said plurality of delay elements, the plurality of time delays provided by said plurality of delay elements being set such that a time lag between any two successive delayed clock signals generated by said plurality of delay elements is less than the shortest one of the plurality of time delays provided by said plurality of delay elements;
• a phase comparator for comparing the phase of either an output of said delay means or a signal associated with the output of said delay means with that of a reference clock signal applied thereto so as to generate a phase difference clock signal indicating the phase difference between them;
• and
• a delay setting circuit for causing said selector to change a selection of one delayed clock signal according to the phase difference signal from said phase comparator in such a manner as to reduce the phase difference.

Clock delay circuitry comprising:

• a plurality of delay elements, each having a different delay time with a smallest difference in delay time between any two of the plurality of delay elements being smaller than the shortest delay element;
• a limit delay element having a delay which is slightly larger than largest of the plurality of delay elements, the limit delay element being connected in parallel with each of the plurality of delay elements and receiving an identical clock signal;
• and
• selection means for selecting a delayed clock signal from either an output of one of the plurality of delay elements or an output of the limit delay element, wherein the delayed clock signal selected by the selection means may have a delay shorter than the smallest delay of any of the plurality of delay elements.