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US 6,184,745 B2Granted
Reference voltage generating circuit
AssigneeLG Semicon Co., Ltd.
InventorTae-Hoon Kim
Life of this patent
Estimating the term…
Abstract
A reference voltage generating circuit generates a reference voltage by using a voltage difference of a PMOS transistor, to thereby exclude the reliability of a back-bias voltage. The reference voltage generating circuit includes a reference voltage generating unit which generates a first reference voltage with respect to a power supply voltage, and a level converting unit which converts the first reference voltage applied from the reference voltage generating unit to a second reference voltage with respect to a ground voltage.
Claims16
A reference voltage generating circuit, comprising:
- a reference voltage generating unit for generating a first reference voltage with respect to a power supply voltage;
- and
- a level converting unit for converting said first reference voltage outputted from said reference voltage generating unit to a second reference voltage with respect to a ground voltage, and
- wherein the second reference voltage remains constant regardless of changes in a back-bias voltage,
- wherein said reference voltage generating unit comprises:
- a first PMOS transistor having a source and a bulk which receive the power supply voltage over a resistor;
- a second PMOS transistor having a source and a bulk which receive the power supply voltage, and a gate which is connected with a gate of said first PMOS transistor and a first output node;
- and
- first and second NMOS transistors each having a bulk for receiving the back-bias voltage, the first NMOS transistor being connected between a drain of the first PMOS transistor and a ground, and the second NMOS transistor being connected between a drain of the second PMOS transistor and the ground, thereby constituting a current mirror.
6 more elements
A reference voltage generating circuit, comprising:
- a reference voltage generating unit for generating a first reference voltage with respect to a power supply voltage by using a voltage difference between a gate and a source of a PMOS transistor;
- the reference voltage generating unit comprising:
- a first PMOS transistor having a source and a bulk which receive the power supply voltage over a resistor,
- a second PMOS transistor having a source and a bulk which receive the power supply voltage, and a gate which is connected with a gate of said first PMOS transistor and a first output node, and
- a first NMOS transistor connected between a drain of the first PMOS transistor and a ground, and a second NMOS transistor connected between a drain of the second PMOS transistor and the ground, thereby constituting a current mirror;
- and
- a level converting unit for converting said first reference voltage supplied from said reference voltage generating unit to a second reference voltage with respect to a ground voltage and maintaining the second reference voltage at a constant value regardless of changes in a back-bias voltage applied to a bulk of the first and the second NMOS transistors, the level converting unit comprising:
- a third PMOS transistor connected between the power supply voltage and a second output node, and having a source which is connected with a bulk thereof and a gate which is connected with the first output node of the reference voltage generating unit;
- and
- at least one diode-type PMOS transistor which is connected between the second output node and the ground.
7 more elements
A reference voltage generating circuit, comprising:
- a first PMOS transistor having a source and a bulk which receive a power supply voltage over a resistor;
- a second PMOS transistor having a source and a bulk which receive the power supply voltage, and a gate which is commonly connected with a gate of the first PMOS transistor and a first output node;
- first and second NMOS transistors which are respectively connected with corresponding drains of the first and the second PMOS transistors and a ground, thereby constituting a current mirror, wherein each bulk of the first and second NMOS transistors receives a back-bias voltage;
- a third PMOS transistor having a source which is connected with a bulk between the power supply voltage and a second output node, and a gate connected with the first output node;
- and
- at least one diode-type PMOS transistor connected between the second output node and the ground.
3 more elements
Dependencies are inferred from the claim text.