Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage

An internal power supply voltage generation circuit comprising:

• comparator circuitry for providing a signal according to a difference between an internal power supply voltage on an internal power supply line and a reference voltage from an output node thereof;
• a current drive element coupled between an external voltage source supplying an externally applied external power supply voltage and said internal power supply line, and responsive to the signal from the output node of said comparator circuitry for causing a current flow between said external voltage source and said internal power supply line;
• and
• level adjust circuitry for adjusting a voltage level of the signal applied from the output node of said comparator circuitry to said current drive element in accordance with the difference between said external power supply voltage and said reference voltage, wherein said level adjust circuitry comprises:
• a comparator stage including (i) a first insulated gate field effect transistor receiving said external power supply voltage at a gate thereof and (ii) a second insulated gate field effect transistor having a current supply ability greater than a current supply ability of said first insulated gate field effect transistor under a condition of the same gate voltage and receiving said reference voltage at a gate thereof, for comparing said external power supply voltage and said reference voltage, and
• a current mirror type current supply stage for supplying a current to said comparator stage.