Variable delay circuit
AssigneeKabushiki Kaisha Toshiba
InventorNorifumi Kobayashi
Life of this patent
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Abstract
A variable delay circuit comprises: a variable delay part having n (≧2) cascade-connected delay parts, each of which has a delay element, a selecting circuit for selecting whether an input signal is allowed to pass through the delay element, and an OR gate for outputting an output of the selected delay element or the input signal; and a control part for selecting at least one of the plurality of delay parts on the basis of desired delay time information to transmit a control signal for operating so that the selecting circuit in the selected delay part selects a corresponding one of the delay elements, wherein a designed delay time value Dk of the delay element of a number k (1≦k≦n) delay part meets the following conditions. Thus, it is possible to provide a smaller circuit scale of a variable delay circuit.
Claims6
A variable delay circuit comprising:
- a variable delay part having n (≧2) cascade-connected delay parts, each of which has a delay element, a selecting circuit for selecting whether an input signal is allowed to pass through said delay element, and an OR gate for outputting an output of the selected delay element or said input signal;
- and
- control means for selecting at least one of said plurality of delay parts on the basis of desired delay time information to transmit a control signal for operating so that the selecting circuit in the selected delay part selects a corresponding one of said delay elements,
- wherein assuming that a variable width of a delay time is Span, a resolution being Res, and absolute and relative errors being da and dr, respectively, then, a designed delay time value Dk of the delay element of a number k (1≦k≦n) delay part meets the following conditions:
- D1=Span/(1−da)/2
- D2=(Span/(1−da)/2)×(1+dr)/2
- when k≧3, D k = { ( Span / ( 1 - da ) / 2 ) × ( 1 + dr ) - ∑ i = 1 k - 1 D i × ( 1 - dr ) } / 2 Span < ∑ i = 1 n ( D i × ( 1 - da ) ) Dn×(1+da)×(1+dr)<Res.
A variable delay circuit comprising:
- a variable delay part having n (≧2) cascade-connected delay parts, each of which has a delay element, a selecting circuit for selecting whether an input signal is allowed to pass through said delay element, and an OR gate for outputting an output of the selected delay element or said input signal;
- and
- control means for selecting at least one of said plurality of delay parts on the basis of desired delay time information to transmit a control signal for operating so that the selecting circuit in the selected delay part selects a corresponding one of said delay elements,
- wherein assuming that a variable width of a delay time is Span, a resolution being Res, the best and worst values of absolute errors of the whole delay time being dab and daw, respectively, and the best and worst values of relative errors of the delay time of a delay element of a number i (1≦i≦n) delay part being drbi and drwi, respectively, then, a designed delay time value Dk of the delay element of a number k (1≦k≦n) delay part meets the following conditions:
- D1=Span/(1−dab)/2
- D2=(Span/(1−dab)/2)×(1+drw1)/2
- when k≧3, D k = { ( Span / ( 1 - dab ) / 2 ) × ( 1 + drwl ) - ∑ i = 1 k - 1 D i × ( 1 - drbi ) } / 2 Span < ∑ i = 1 n ( D i × ( 1 - dab ) ) Dn×(1+daw)×(1+drwn)<Res.
A variable delay circuit comprising:
- a variable delay part having n (≧2) cascade-connected delay parts, each of which has a delay element, a selecting circuit for selecting whether an input signal, is allowed to pass through said delay element, and an OR gate for outputting an output of the selected delay element or said input signal;
- and
- control means for selecting at least one of said plurality of delay parts on the basis of desired delay time information to transmit a control signal for operating so that the selecting circuit in the selected delay part selects a corresponding one of said delay elements,
- wherein assuming that a variable width of a delay time is Span, a resolution being Res, the best and worst values of absolute errors of the whole delay time being dab and daw, respectively, the best and worst values of relative errors of the delay time of a delay element of a number i (1≦i≦n) delay part being drbi and drwi, respectively, and OPT being a positive number, then, a designed delay time value Dk of the delay element of a number k (1≦k≦n) delay part meets the following conditions:
- D1=Span/(1−dab)/2−OPT
- D2={Span/(1−dab)/2)×(1+drw1) −OPT}/2
- when k≧3, D k = { ( Span / ( 1 - dab ) / 2 ) × ( 1 + drwl ) - OPT - ∑ i = 1 k - 1 D i × ( 1 - drbi ) } / 2 Span < ∑ i = 1 n ( D i × ( 1 - dab ) ) Dn (1+daw)×(1drwn)<Res.
Dependencies are inferred from the claim text.