Digital phase locked loop

A phase locked loop device for generating an output signal having a predetermined phase relationship relative to an input signal, said device comprising:

• means for generating a multiplicity of candidate clocks signals which are all at the same clock fequency but have different phases;
• means for sampling each of said candidate clock signals in response to a predetermined edge of the input signal to produce a plurality of sample values each related to a respective one of said candidate clock signals;
• gating means for comparing sample values corresponding to said candidate clock signals to produce a multiplicity of gate outputs of which one indicates the location of a predetermined change in sample value from one candidate signal to the next;
• an encoder for converting said gated outputs into a coded address related to said location;
• a multiplexer for receiving said candidate clock signals and for selecting for the output signal a candidate clock signal in response to a clock address;
• and
• clock phase adjustment means including means for comparing said clock address and said coded address to produce a digital error signal and means for modifying said clock address in response to said digital error signal.