Clock synchronizing circuit

A clock synchronizing circuit, comprising:

• a first phase comparator that receives a time-delayed external clock signal and a feedback clock signal, determines a first phase difference between the time-delayed external clock signal and the feedback clock signal, and outputs a first phase error detecting signal;
• a second phase comparator that receives a first external clock signal and a time-delayed feedback clock signal, determines a second phase difference between the first external clock signal and the time-delayed feedback clock signal, and outputs a second phase error detecting signal;
• a phase compensator that inputs the first external clock signal and outputs a second external clock signal, wherein the phase compensator has a first mode of operation, in which the phase compensator phase-compensates the first external clock signal to generate the second external clock signal, and a second mode of operation, in which the phase compensator does not phase-compensate the first external clock signal, wherein the first and second modes are selectable based on the first and second phase error detecting signals;
• and
• a charge pump that generates a charge and adjusts a magnitude of the charge in response to the first and second phase error detecting signals.

A method of synchronizing a clock, comprising:

• determining a first phase difference between a time-delayed external clock signal and a feedback clock signal;
• determining a second phase difference between an external clock signal and a time-delayed feedback clock signal;
• determining, based on the first and second phase differences, if the external clock signal and the feedback clock signal are substantially in phase;
• generating and adjusting a magnitude of a charge in response to the first and second phase differences;
• compensating, in accordance with the magnitude of the charge, a phase of the external clock signal if the external clock signal and the feedback clock signal are not substantially in phase;
• and
• not compensating the phase of the external clock signal if the external clock signal and the feedback clock signal are substiantially in phase.