Setting the common mode level of a differential charge pump output

A circuit comprising:

• first and second filter nodes;
• first and second bypass nodes corresponding to the first and second filter nodes, respectively;
• a charge transfer circuit having at least one charge transfer node that is alternately coupled through a low impedance path to one of the filter nodes and a corresponding one of the bypass nodes;
• and
• first trimmable buffer including a first amplifier having a load and a first output, the first output being coupled to the first bypass node, the first amplifier being configured to buffer the voltage on the first filter node at the first bypass node, and a differential amplifier sharing the load of the first amplifier to change the voltage at the first bypass node according to a difference between a control voltage and a common mode voltage of the differential voltage between the first and second filter nodes.

An electronic system comprising:

• system bus;
• processor and memory coupled to the bus;
• and
• bus interface device capable of recovering a clock signal from signals received via a bus, and to deliver data from the bus to the system bus, the bus interface device includes a phase locked loop having a phase detector, charge pump and filter, and voltage controlled oscillator (VCO), the phase detector to generate phase error signals in response to comparing an input phase to an output phase, the charge pump and filter capable of generating a differential voltage proportional to the phase error signals, and the VCO to generate an oscillatory output signal whose frequency is proportional to the differential voltage, and wherein the charge pump includes first and second filter nodes, first and second bypass nodes corresponding to the first and second filter nodes, respectively, a charge transfer circuit having at least one charge transfer node that is capable of being alternately coupled through a low impedance path switching means to one of the filter nodes and a corresponding one of the bypass nodes, and first and second amplifiers to buffer the voltages on the first and second filter nodes and provide first and second output voltages to the first and second bypass nodes, respectively, wherein the output voltage of each amplifier is adjusted according to a difference between a control voltage and a common mode voltage of the first and second filter nodes, the first and second filter nodes being coupled to an input of the VCO.