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US 6,184,729 B2Granted
Low ground bounce and low power supply bounce output driver
AssigneeNational Semiconductor Corporation
InventorRonald Pasqualini
Life of this patent
Estimating the term…
Abstract
Ground bounce and power supply bounce are reduced in an output driver by utilizing a plurality of p-channel and n-channel transistors which are connected to an output pad, by sequentially turning off the p-channel transistors before sequentially turning on the n-channel transistors, and by sequentially turning off the n-channel transistors before sequentially turning on the p-channel transistors.
Claims15
An output driver comprising:
- a first delay circuit having:
- an input connected to receive a first input signal, the first input signal having a logic state, and
- a plurality of first delay stages that output a corresponding plurality of delayed first signals which change logic states at different times after the logic state of the first input signal changes state, a first delay stage of the plurality of first delay stages having:
- a first inverter, the first inverter having a first transistor and a second transistor connected to the first transistor, the first transistor having a width-to-length (W/L) ratio, the second transistor having a W/L ratio, the W/L ratio of the first transistor being greater than the W/L ratio of the second transistor;
- a second inverter connected to the first inverter, the second inverted having a first transistor and a second transistor connected to the first transistor of the second inverter, the first transistor of the second inverter having a W/L ratio, the second transistor of the second inverter having a W/L ratio, the W/L ratio of the first transistor of the second inverter being substantially equal to the W/L ratio of the second transistor of the second inverter;
- a plurality of first driver transistors which are each connected to receive a delayed first input signal;
- a second delay circuit having:
- an input connected to receive a second input signal, the second input signal having a logic state, and
- a plurality of second delay stages that output a corresponding plurality of delayed second signals which change logic states at different times after the logic state of the second input signal changes state;
- and
- a plurality of second driver transistors which are each connected to the first driver transistors and to receive a delayed second input signal.
8 more elements
An output driver comprising:
- a first delay circuit having:
- an input connected to receive a first input signal, the first input signal having a logic state, and
- a plurality of first delay stages that output a corresponding plurality of delayed first signals which change logic states at different times after the logic state of the first input signal changes state, a first delay stage of the plurality of first delay stages having a first inverter, the first inverter having a first transistor and a second transistor connected to the first transistor, the first transistor having a width-to-length (W/L) ratio, the second transistor having a W/L ratio, the W/L ratio of the first transistor being greater than the W/L ratio of the second transistor;
- a plurality of first driver transistors which are each connected to receive a delayed first input signal;
- second delay circuit having:
- an input connected to receive a second input signal, the second input signal having a logic state, and
- a plurality of second delay stages that output a corresponding plurality of delayed second signals which change logic states at different times after the logic state of the second input signal changes state, a second delay stage of the plurality of second delay stages of the second delay circuit includes a first inverter having a first transistor and a second transistor connected to the first transistor of the first inverter of the second delay stage, the first transistor of the first inverter of the second delay stage having a W/L ratio, the second transistor of the first inverter of the second delay stage having a W/L ratio, the W/L ratio of the first transistor of the first inverter of the second delay stage being less than the W/L ratio of the second transistor of the first inverter of the second delay stage;
- and
- a plurality of second driver transistors which are each connected to the first driver transistors and to receive a delayed second input signal.
6 more elements
Dependencies are inferred from the claim text.