Latch-type sense amplifier for amplifying low level differential input signals

A sense amplifier, comprising:

• a) a first input signal line and a second input signal line for receiving a first and a second input signal, respectively, said first and second input signals forming a differential input signal pair;
• b) a first transistor of a first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal electrically coupled to the first input signal line for receiving said first input signal;
• c) a second transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal electrically coupled to the second input signal line for receiving said second input signal;
• d) said third terminal of said second transistor electrically connected to said second terminal of said first transistor and forming a first output;
• e) said third terminal of said first transistor electrically coupled connected to said second terminal of said second transistor and forming a second output;
• f) said first and second outputs for supplying an output signal and its inverse;
• g) a first switching circuit for connecting said third terminal of said first and second transistors to a first voltage source;
• h) a second switching circuit for connecting said third terminal of said first and second transistors to said first voltage source;
• and
• a third switching circuit for connecting said first terminal of said first transistor to said first input signal line, and for connecting said first terminal of said second transistor to said second input signal line, wherein the first output switches from a high level to a low level and the second output remains at said high level, when the input signal pair reaches a threshold differential.

A sense amplifier, comprising:

• a) a first input signal line and a second input signal line for receiving a first and a second input signal, Respectively, said first and second input signals forming a differential input signal pair;
• b) a first transistor of a first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal electrically coupled to the first input signal line for receiving said first input signal;
• c) a second transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal electrically coupled to the second input signal line for receiving said second input signal;
• d) said third terminal of said second transistor electrically connected to said second terminal of said first transistor and forming a first output;
• e) said third terminal of said first transistor electrically coupled connected to said second terminal of said second transistor and forming a second output;
• f) said first and second outputs for supplying an output signal and its inverse;
• g) a first switching circuit for connecting said third terminal of said first and second transistors to a first voltage source;
• h) a second switching circuit for connecting said third terminal of said first and second transistors to said first voltage source;
• and
• a third input signal line and a fourth input signal line for receiving a third and a fourth input signal, respectively, said third and fourth input signals forming another differential input signal pair, said first terminal of said first transistor electrically coupled to the third input signal line for receiving said third input signal, said first terminal of said second transistor electrically coupled to the fourth input signal line for receiving said fourth input signal, wherein the first output switches from a high level to a low level and the second output remains at said high level, when the input signal pair reaches a threshold differential.

A sense amplifier, comprising:

• a) a first input signal line and a second input signal line for receiving a first and a second input signal, respectively, said first and second input signals forming a differential input signal pair;
• b) a first transistor of a first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal electrically coupled to the first input signal line for receiving said first input signal;
• c) a second transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal electrically coupled to the second input signal line for receiving said second input signal;
• d) a third transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said third transistor connected to said third terminal of said first transistor, said second terminal of said third transistor connected to a first control signal;
• e) a fourth transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said fourth transistor connected to said third terminal of said second transistor, said second terminal of said fourth transistor connected to said second control signal;
• f) said third terminal of said fourth transistor electrically connected to said second terminal of said first transistor and forming a first output;
• e) said third terminal of said third transistor electrically coupled connected to said second terminal of said second transistor and forming a second output;
• f) said first and second outputs for supplying an output signal and its inverse;
• g) a first switching circuit for connecting said third terminal of said third and fourth transistors to a first voltage source;
• and
• h) a second switching circuit for connecting said third terminal of said third and fourth transistors to said first voltage source;
• wherein the first output switches from a high level to a low level and the second output remains at said high level, when the input signal pair reaches a threshold differential.

The amplifier of claim, 13, wherein the first switching circuit includes

• a fifth transistor of a second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said fifth transistor connected to said third terminal of said third transistor, said third terminal of said fifth transistor connected to said first voltage source, said second terminal of said fifth transistor connected to a second control signal, and
• an sixth transistor of said second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said sixth transistor connected to said third terminal of said fourth transistor, said third terminal of said sixth transistor connected to said first voltage source, said second terminal of said sixth transistor connected to said second control signal;
• and wherein the second switching circuit includes
• a seventh transistor of said second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said seventh transistor connected to said third terminal of said third transistor, said third terminal of said seventh transistor connected to said first voltage source, said second terminal of said seventh transistor connected to said third terminal of said fourth transistor, and
• an eighth transistor of said second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said eighth transistor connected to said third terminal of said fourth transistor, said third terminal of said eighth transistor connected to said first voltage source, said second terminal of said eighth transistor connected to said third terminal of said third transistor.

The amplifier of claim, 18, further comprising:

• a fifth transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said third terminal of said fifth transistor connected to said first terminal of said third transistor, said second terminal of said fifth transistor connected to said first terminal of said fourth transistor;
• a sixth transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said third terminal of said sixth transistor connected to said first terminal of said fourth transistor, said second terminal of said sixth transistor connected to said first terminal of said third transistor;
• and
• a seventh transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said seventh transistor connected to a second voltage source, said third terminal of said seventh transistor connected to both said first terminal of said fifth transistor and said first terminal of said sixth transistor, said second terminal of said seventh transistor connected to said second terminals of said third and fourth transistors.

A sense amplifier, comprising:

• a) a first input signal line and a second input signal line for receiving a first and a second input signal, respectively, said first and second input signals forming a differential input signal pair;
• b) a first transistor of a first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal electrically coupled to the first input signal line for receiving said first input signal;
• c) a second transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal electrically coupled to the second input signal line for receiving said second input signal;
• d) said third terminal of said second transistor electrically connected to said second terminal of said first transistor and forming a first output;
• e) said third terminal of said first transistor electrically coupled connected to said second terminal of said second transistor and forming a second output;
• f) said first and second outputs for supplying an output signal and its inverse;
• g) a first switching circuit for connecting said third terminal of said first and second transistors to a first voltage source;
• and
• h) a second switching circuit for connecting said third terminal of said first and second transistors to said first voltage source;
• wherein the first output switches from a high level to a low level and the second output remains at said high level, when the input signal pair reaches a threshold differential, wherein the first switching circuit includes
• a third transistor of a second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said third transistor connected to said third terminal of said first transistor, said third terminal of said third transistor connected to said first voltage source, said second terminal of said third transistor for receiving a control signal;
• and
• a fourth transistor of said second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said fourth transistor connected to said third terminal of said second transistor, said third terminal of said fourth transistor connected to said first voltage source, said second terminal of said fourth transistor for receiving said control signal;
• and wherein the second switching circuit includes
• a fifth transistor of said second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said fifth transistor connected to said third terminal of said first transistor, said third terminal of said fifth transistor connected to said first voltage source, said second terminal of said fifth transistor connected to said third terminal of said second transistor, and
• a sixth transistor of said second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said sixth transistor connected to said third terminal of said second transistor, said third terminal of said sixth transistor connected to said first voltage source, said second terminal of said sixth transistor connected to said third terminal of said first transistor;
• and
• further comprising a third input signal line and a fourth input signal line for receiving a third and a fourth input signal, respectively, said third and fourth input signals forming another differential input signal pair, said first terminal of said first transistor electrically coupled to the third input signal line for receiving said third input signal, said first terminal of said second transistor electrically coupled to the fourth input signal line for receiving said fourth input signal.

A sense amplifier, comprising:

• a) a first input signal line and a second input signal line for receiving a first and a second input signal, respectively, said first and second input signals forming a differential input signal pair;
• b) a first transistor of a first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal electrically coupled to the first input signal line for receiving said first input signal;
• c) a second transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal electrically coupled to the second input signal line for receiving said second input signal;
• d) said third terminal of said second transistor electrically connected to said second terminal of said first transistor and forming a first output;
• e) said third terminal of said first transistor electrically coupled connected to said second terminal of said second transistor and forming a second output;
• f) said first and second outputs for supplying an output signal and its inverse;
• g) a first switching circuit for connecting said third terminal of said first and second transistors to a first voltage source;
• and
• h) a second switching circuit for connecting said third terminal of said first and second transistors to said first voltage source;
• wherein the first output switches from a high level to a low level and the second output remains at said high level, when the input signal pair reaches a threshold differential, wherein the first switching circuit includes
• a third transistor of a second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said third transistor connected to said third terminal of said first transistor, said third terminal of said third transistor connected to said first voltage source, said second terminal of said third transistor for receiving a control signal;
• and
• a fourth transistor of said second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said fourth transistor connected to said third terminal of said second transistor, said third terminal of said fourth transistor connected to said first voltage source, said second terminal of said fourth transistor for receiving said control signal;
• and wherein the second switching circuit includes
• a fifth transistor of said second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said fifth transistor connected to said third terminal of said first transistor, said third terminal of said fifth transistor connected to said first voltage source, said second terminal of said fifth transistor connected to said third terminal of said second transistor, and
• a sixth transistor of said second conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said sixth transistor connected to said third terminal of said second transistor, said third terminal of said sixth transistor connected to said first voltage source, said second terminal of said sixth transistor connected to said third terminal of said first transistor;
• and further comprising
• a third switching circuit for connecting said first terminal of said first transistor to said first input signal line, and for connecting said first terminal of said second transistor to said second input signal line,
• wherein said third switching circuit comprises:
• a seventh transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said seventh transistor connected to said first input signal line, said third terminal of said seventh transistor connected directly to said first terminal of said first transistor, said second terminal of said seventh transistor for receiving a control signal;
• and
• an eighth transistor of said first conductivity type having a first and a third spaced apart terminals, and a second terminal for controlling the flow of current between the first and the third terminals, said first terminal of said eighth transistor connected to said second input signal line, said third terminal of said eighth transistor connected directly to said first terminal of said second transistor, said second terminal of said eighth transistor connected to said second terminal of said seventh transistor.