CMOS voltage comparator capable of operating with small input voltage difference

A method for comparing input voltages having a small difference, the method comprising:

• receiving a first input voltage and a second input voltage for comparison;
• receiving a strobe signal that indicates a transition between a reset mode and a comparison mode;
• providing a comparison element to allow the strobe signal to operate to prevent load transistors from any charge conduction during the reset mode, which reduces threshold mismatch in the load transistors during the comparison mode;
• and
• determining which of the first and second input voltages is larger.

A voltage comparator circuit having a reset mode and a comparison mode, the circuit comprising:

• a power supply configured to supply a supply voltage and a ground voltage;
• a common-source differential amplifier having a pair of input transistors configured to receive a first input voltage and a second input voltage applied at a gate terminal of each input transistor, the pair of input transistors operating to draw current from the supply voltage that is proportional to the input voltages;
• a pair of cross-coupled load transistors operating as loads for the input transistors and passing current to the common-drain node, where more current is passed by a load transistor whose gate terminal is drawn by the input transistor with higher input voltage;
• a pair of switches, each connected across source and drain terminals of each of said pair of cross-coupled load transistors, where said pair of switches operates to prevent any charge or current conduction through the load transistors during the reset mode, which reduces threshold mismatch in the load transistors during the comparison mode;
• and
• a third switch connected from the common-source terminal of the input transistors to the ground voltage.

A CMOS active pixel image sensor system comprising:

• an image pixel array;
• a timing and control element coupled to the image pixel array to control processing of photo-detector data;
• and
• an analog to digital converter coupled to the image pixel array and including a voltage comparator circuit including:
• a pair of switching elements;
• a first input element that receives input voltages for comparison;
• a second input element that receives a strobe signal that indicates a transition from a reset mode to a comparison mode;
• and
• a comparison element coupled to the first and second input elements to receive the input voltages and configured to determine which of the input voltages is larger, said comparison element including:
• a pair of source-coupled input transistors configured to draw current from a supply voltage, the current being proportional to the input voltages applied at the gate terminals of the input transistors, and
• a pair of cross-coupled load transistors configured to pass the current drawn by the input transistors, where more current is passed by the load transistor whose gate terminal is drawn by the input transistor with higher input voltage,
• where each of said pair of switching elements are arranged across source and drain terminals of each of said pair of cross-coupled load transistors to prevent any charge or current conduction through the load transistors during the reset mode, which reduces threshold mismatch in the load transistors during the comparison mode.

A CMOS image sensor camera system comprising:

• an image pixel array;
• a timing and control element coupled to the image pixel array to control processing of photo-detector data;
• an analog-to-digital converter coupled to the image pixel array and including a voltage comparator circuit including:
• a pair of switching elements;
• a first input element that receives input voltages for comparison;
• a second input element that receives a strobe signal that indicates a transition from a reset mode to a comparison mode;
• and
• a comparison element coupled to the first and second input elements to receive the input voltages and configured to determine which of the input voltages is larger, said comparison element including:
• a pair of source-coupled input transistors configured to draw current from a supply voltage, the current being proportional to the input voltages applied at the gate terminals of the input transistors, and
• a pair of cross-coupled load transistors configured to pass the current drawn by the input transistors, where more current is passed by the load transistor whose gate terminal is drawn by the input transistor with higher input voltage,
• where each of said pair of switching elements are arranged across source and drain terminals of each of said pair of cross-coupled load transistors to prevent any charge or current conduction through the load transistors during the reset mode, which reduces threshold mismatch in the load transistors during the comparison mode;
• an image display device configured to receive a digitized image from the analog-to-digital converter and display the image on the image display device.