Internal voltage generating circuit of a semiconductor device using test pad and a method thereof

An internal voltage generating circuit in semiconductor device for converting an external power voltage applied from the semiconductor device into an internal voltage for driving an internal circuit, comprising:

• a plurality of test power voltage pads, each of which can be selectively applied with the external power voltage and a ground voltage during test;
• a fuse programmable control signal generator coupled to the plurality of test power voltage pads, for generating a control signal according to the signals applied to the plurality of said test power voltage pads during test, and for generating the control signal according to fuse-programmed state after at least one fuse included therein is programmed;
• a reference voltage generator for receiving the external power voltage so as to produce a reference voltage having a predetermined level;
• a voltage trimming unit for trimming the reference voltage in accordance with the output of the fuse programmable control signal generator;
• a stress voltage generator for receiving the external power voltage and generating a stress voltage proportional to the external power voltage;
• and
• a reference voltage modifying unit for inputting the trimmed reference voltage which is output of said voltage level trimming unit and the stress voltage, and for producing the trimmed reference voltage when the external power voltage is equal to or lower than a predetermined level and for producing the stress voltage when the external power voltage is higher than the predetermined level.

An internal voltage generating circuit in semiconductor device for converting an external power voltage applied from the semiconductor device into an internal voltage for driving an internal circuit, comprising:

• a plurality of test power voltage pads, each of which can be selectively applied with the external power voltage and a ground voltage during test;
• a fuse programmable control signal generator coupled to the plurality of test power voltage pads, for generating a control signal according to the signals applied to the plurality of said test sower voltage Dads during test, and for generating the control signal according to fuse-programmed state after at least one fuse included therein is programmed;
• a reference voltage generator for receiving the external power voltage so as to produce a reference voltage having a predetermined level;
• and
• a voltage trimming unit for trimming the reference voltage in accordance with the output of the fuse programmable control signal generator;
• wherein said fuse programmable control signal generator comprises:
• a fuse circuit block including a plurality of fuse circuits, each of the fuse circuits including a programmable fuse and being coupled to the corresponding test power voltage pad, respectively;
• a decoding unit for decoding the output of the fuse circuit block so as to produce the control signal.

An internal voltage generating circuit in semiconductor device for converting an external power voltage applied from the semiconductor device into an internal voltage for driving an internal circuit, comprising:

• a plurality of test power voltage pads, each of which can be selectively applied with the external power voltage and a ground voltage during test;
• a fuse programmable control signal generator coupled to the plurality of test power voltage pads, for generating a control signal according to the signals applied to the plurality of said test power voltage pads during test, and for generating the control signal according to fuse-programmed state after at least one fuse included therein is programmed;
• a reference voltage generator for receiving the external power voltage so as to produce a reference voltage having a predetermined level;
• and
• a voltage trimming unit for trimming the reference voltage in accordance with the output of the fuse programmable control signal generator,
• wherein said voltage level trimming unit comprises:
• an input node for inputting a voltage to be trimmed;
• an output node for outputting the trimmed reference voltage the level of which is trimmed;
• a plurality of resistors coupled in series between said input node and said output node;
• and
• a plurality of transfergates, one of which is coupled between said input node and said output node, the others of which are coupled in parallel between the connection point of said resistors and said output node, respectively, each of the transfer gates being turned on/off in response to corresponding control signal.

An internal voltage generating circuit in semiconductor device for converting an external power voltage applied from the semiconductor device into an internal voltage for driving an internal circuit, comprising:

• a plurality of test power voltage pads, each of which can be selectively applied with the external power voltage and a ground voltage during test;
• a fuse programmable control signal generator coupled to the plurality of test power voltage pads, for generating a control signal according to the signals applied to the plurality of said test power voltage pads during test, and for generating the control signal according to fuse-programmed state after at least one fuse included therein is programmed;
• a reference voltage generator for receiving the external power voltage so as to produce a reference voltage having a predetermined level;
• and
• a voltage trimming unit for trimming the reference voltage in accordance with the output of the fuse programmable control signal generator;
• wherein said fuse programmable control signal generator comprises:
• a test mode signal generator for generating a test mode signal representing whether the operation mode of the semiconductor device is test mode;
• a pseudo fuse circuit block activated when the test mode signal represents that the operation mode is test mode, said pseudo fuse circuit block producing a positive output signal (CUT) and a negative output signal (CUTB) based on the signals applied to said plurality of test power voltage pads;
• a fuse circuit block activated when the test mode signal represents that the operation mode is not test mode and including a plurality of fuses, said fuse circuit block producing the positive output signal and the negative output signal based on the programmed state of the plurality of fuses included therein;
• and
• a decoding unit coupled to both said pseudo fuse circuit block and said fuse circuit block so as to decode the positive output and the negative output.

A method for generating an internal voltage of semiconductor device by converting an external power voltage applied to the semiconductor device, said internal voltage being used for driving an internal circuit included in the semiconductor device, said method comprising the steps of:

• generating a reference voltage having a predetermined level based on the external power voltage;
• generating an internal power voltage based on the reference voltage;
• measuring the internal power voltage;
• comparing the measured internal power voltage with a preferred internal power voltage;
• generating a trimming control signal by selectively applying the external power voltage or a ground voltage through a plurality of test power voltage pads, based on the result of the step for comparing;
• generating a trimmed reference voltage by trimming the level of the reference voltage in response to the trimming control signal;
• and
• generating a trimmed internal power voltage based on the trimmed reference voltage.